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/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-hsfll-global.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic Global HSFLL clock.
7 The lowest supported clock frequency is the default
8 clock frequency.
13 compatible = "nordic,nrf-hsfll-global";
15 #clock-cells = <0>;
16 clock-frequency = <320000000>;
17 supported-clock-frequencies = <64000000
23 compatible: "nordic,nrf-hsfll-global"
26 - "base.yaml"
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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Desp32c6_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
15 /* Supported CPU frequencies */
20 /* Supported XTAL Frequencies */
24 /* Supported RTC fast clock sources */
28 /* Supported RTC slow clock frequencies */
34 /* RTC slow clock frequencies */
79 /* Peripherals clock managed by the modem_clock driver must be listed last */
Desp32c2_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
15 /* Supported CPU frequencies */
22 /* Supported XTAL frequencies */
27 /* Supported RTC fast clock sources */
31 /* Supported RTC slow clock sources */
36 /* RTC slow clock frequencies */
54 #define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */
Desp32c3_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
15 /* Supported CPU frequencies */
20 /* Supported XTAL frequencies */
24 /* Supported RTC fast clock sources */
28 /* Supported RTC slow clock sources */
34 /* RTC slow clock frequencies */
Desp32s2_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
16 /* Supported PLL CPU frequencies */
22 /* Supported XTAL frequencies */
25 /* Supported RTC fast clock sources */
29 /* Supported RTC slow clock sources */
35 /* RTC slow clock frequencies */
Desp32_clock.h5 * SPDX-License-Identifier: Apache-2.0
11 /* Supported CPU clock Sources */
17 /* Supported PLL CPU frequencies */
23 /* Supported XTAL frequencies */
28 /* Supported RTC fast clock sources */
32 /* Supported RTC slow clock sources */
38 /* RTC slow clock frequencies */
Desp32s3_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
15 /* Supported PLL CPU frequencies */
21 /* Supported XTAL frequencies */
25 /* Supported RTC fast clock sources */
29 /* Supported RTC slow clock sources */
35 /* RTC slow clock frequencies */
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
36 "active-channel" (single channel mode).
38 true = Auto-Scan conversions as selected by "rr-sequence"
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/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
8 #include "clock.h"
16 /* List of supported CCLK frequencies */
24 /* Define 48 MHz and 96 MHz CCLK clock options (not present in HAL) */
47 #error "Wrong value for power-mode parameter"
56 #error "Wrong value for vbat-type parameter"
59 /* Check System Clock value. */
66 #error "Unsupported clock-frequency. Supported values: 16, 24, 32, 48, 64 and 96 MHz"
109 /* Init Machine Timer source clock: 32 KHz RC */ in soc_early_init_hook()
/Zephyr-latest/soc/arm/beetle/
Dsoc_pll.h4 * SPDX-License-Identifier: Apache-2.0
21 * - PLL_OUTPUTDIV [9:8]
22 * - PLL_INPUTDIV [20:16]
23 * - PLL_FEEDDIV [30:24]
30 * -----------------------
39 * BEETLE PLL derived clock is prescaled [1-16]
50 /* BEETLE PLL Supported Frequencies */
/Zephyr-latest/subsys/usb/device_next/class/
Dusbd_uac2.c2 * Copyright (c) 2023-2024 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
37 * requires 6 bytes) and feedback endpoint (4 bytes on High-Speed, 3 bytes on
38 * Full-Speed). Because the total number of endpoints is really small (typically
40 * the USB specification itself is 30 non-control endpoints). Therefore, the
51 /* A.14 Audio Class-Specific Request Codes */
56 /* A.17.1 Clock Source Control Selectors */
60 #define CONTROL_ATTRIBUTE(setup) (setup->bRequest)
61 #define CONTROL_ENTITY_ID(setup) ((setup->wIndex & 0xFF00) >> 8)
62 #define CONTROL_SELECTOR(setup) ((setup->wValue & 0xFF00) >> 8)
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_mcux.c4 * SPDX-License-Identifier: Apache-2.0
20 /* Max output frequency of DPHY bit clock */
56 * bit clock for a given target frequency, such that the DPHY clock in dsi_mcux_best_clock()
59 * configure the DPHY to output the closest realizable clock frequency in dsi_mcux_best_clock()
110 * frequencies in dsi_mcux_best_clock()
114 cm = (vco_freq + (refclk_cn_freq - 1)) / refclk_cn_freq; in dsi_mcux_best_clock()
132 /* SKIP frequencies less than target frequency. in dsi_mcux_best_clock()
138 if ((cand_freq - target_freq) < best_diff) { in dsi_mcux_best_clock()
140 best_diff = (cand_freq - target_freq); in dsi_mcux_best_clock()
161 const struct display_mcux_mipi_dsi_config *config = dev->config; in dsi_mcux_attach()
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/Zephyr-latest/dts/common/nordic/
Dnrf54h20.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
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/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dboard.c2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
28 #define PMIC_SETTLING_TIME 2000U /* in micro-seconds */
64 /* System clock frequency. */
80 /* Frequency exceed max supported */ in board_calc_volt_level()
84 volt = sw1_volt[i - 1U]; in board_calc_volt_level()
128 return -ERANGE; in board_pmic_change_mode()
132 if (ret != -EPERM) { in board_pmic_change_mode()
142 /* Changes power-related config to preset profiles, like clocks and VDDCORE voltage */
168 return -EINVAL; in power_manager_set_profile()
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/Zephyr-latest/drivers/sdhc/
Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
97 /* We have two clock divider stages:
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
100 * frequencies 160MHz/(N + 1), where 0 < N < 16, I.e. from 10 to 80 MHz.
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
132 /* Wait for the clock to propagate */ in sdmmc_host_set_clk_div()
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/Zephyr-latest/drivers/audio/
Ddmic_nrfx_pdm.c4 * SPDX-License-Identifier: Apache-2.0
52 k_mem_slab_free(drv_data->mem_slab, drv_data->mem_slab_buffer); in free_buffer()
53 LOG_DBG("Freed buffer %p", drv_data->mem_slab_buffer); in free_buffer()
58 drv_data->stopping = true; in stop_pdm()
59 nrfx_pdm_stop(drv_data->pdm); in stop_pdm()
64 struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; in event_handler()
65 const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; in event_handler()
69 if (evt->buffer_requested) { in event_handler()
73 ret = k_mem_slab_alloc(drv_data->mem_slab, &drv_data->mem_slab_buffer, K_NO_WAIT); in event_handler()
78 ret = dmm_buffer_in_prepare(drv_cfg->mem_reg, drv_data->mem_slab_buffer, in event_handler()
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/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
40 /* common clock control device node for all Microchip XEC chips */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
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Dspi_nrfx_spim.c2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
102 struct spi_nrfx_data *dev_data = dev->data; in request_clock()
103 const struct spi_nrfx_config *dev_config = dev->config; in request_clock()
106 if (!dev_config->clk_dev) { in request_clock()
111 dev_config->clk_dev, &dev_config->clk_spec, in request_clock()
114 LOG_ERR("Failed to request clock: %d", error); in request_clock()
118 dev_data->clock_requested = true; in request_clock()
129 struct spi_nrfx_data *dev_data = dev->data; in release_clock()
130 const struct spi_nrfx_config *dev_config = dev->config; in release_clock()
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/Zephyr-latest/drivers/pwm/
Dpwm_stm32.c6 * SPDX-License-Identifier: Apache-2.0
24 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
31 /* L0 series MCUs only have 16-bit timers and don't have below macro defined */
39 * @brief Capture state when in 4-channel support mode
71 * This is not the case when using four-channel-support.
79 /** Timer clock (Hz). */
199 * @brief Check if LL counter mode is center-aligned.
203 * @return `true` when center-aligned, otherwise `false`.
213 * Obtain timer clock speed.
215 * @param pclken Timer clock control subsystem.
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/Zephyr-latest/include/zephyr/net/
Dieee802154_radio.h5 * SPDX-License-Identifier: Apache-2.0
12 * @note All references to the standard in this file cite IEEE 802.15.4-2020.
38 * @details This API provides a common representation of vendor-specific
44 * - a basic, mostly PHY-level driver API to be implemented by all drivers,
45 * - several optional MAC-level extension points to offload performance
51 * offloading to vendor-specific hardware or firmware features may be required
56 * Whether or not MAC-level offloading extension points need to be implemented
60 * @note All section, table and figure references are to the IEEE 802.15.4-2020
67 * @name IEEE 802.15.4-2020, Section 6: MAC functional description
90 * @name IEEE 802.15.4-2020, Section 8: MAC services
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/Zephyr-latest/include/zephyr/bluetooth/audio/
Daudio.h8 * Copyright (c) 2020-2024 Nordic Semiconductor ASA
10 * SPDX-License-Identifier: Apache-2.0
67 /** Supported sampling frequencies */
70 /** Supported frame durations */
73 /** Supported audio channel counts */
76 /** Supported octets per codec frame */
79 /** Supported maximum codec frames per SDU */
83 /** @brief Supported frequencies bitfield */
135 /** @brief Supported frame durations bitfield */
164 /** Supported audio capabilities channel count bitfield */
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/Zephyr-latest/doc/releases/
Drelease-notes-4.0.rst15 is now the standard way to provide device-specific protection to data at rest. (:github:`76222`)
18 :ref:`ZMS <zms_api>` is a new key-value storage subsystem compatible with all non-volatile storage
25 runtime configuration through vendor specific APIs. Initially the :dtcompatible:`nordic,nrf-comp`,
26 :dtcompatible:`nordic,nrf-lpcomp` and :dtcompatible:`nxp,kinetis-acmp` are supported.
31 Initially implemented drivers include a simple :dtcompatible:`zephyr,gpio-steppers` and a complex
32 sensor-less stall-detection capable with integrated ramp-controller :dtcompatible:`adi,tmc5041`.
40 interfaces, audio interfaces, and codecs being supported.
50 directory for :zephyr:code-sample-category:`code samples <samples>`.
54 :ref:`shields <shields_added_in_zephyr_4_0>` are supported in Zephyr 4.0.
70 * :cve:`2024-8798`: Under embargo until 2024-11-22
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.c4 * SPDX-License-Identifier: Apache-2.0
22 #define dai_set_drvdata(dai, data) (dai->priv_data = data)
23 #define dai_get_drvdata(dai) dai->priv_data
24 #define dai_get_plat_data(dai) dai->ssp_plat_data
25 #define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
26 #define dai_get_ftable(dai) dai->ssp_plat_data->ftable
27 #define dai_get_fsources(dai) dai->ssp_plat_data->fsources
28 #define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
29 #define dai_base(dai) dai->ssp_plat_data->base
30 #define dai_ip_base(dai) dai->ssp_plat_data->ip_base
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