| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_common.h | 297 * @brief Checks whether the current control transfer stage is Data Stage OUT
301 * @return true if stage is Data Stage OUT
306 * @brief Checks whether the current control transfer stage is Data Stage IN
310 * @return true if stage is Data Stage IN
315 * @brief Checks whether the current control transfer stage is Status IN
319 * @return true if stage is Data Stage IN
324 * @brief Checks whether the current control transfer stage is Status OUT
328 * @return true if stage is Data Stage OUT
333 * @brief Checks whether the current control transfer stage is Status no-data
337 * @return true if stage is Status no-data
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| D | udc_common.c | 746 data->stage = CTRL_PIPE_STAGE_SETUP; in udc_enable()
923 /* Allocate buffer for data stage IN */ in udc_ctrl_submit_s_in_status()
961 return data->stage == CTRL_PIPE_STAGE_DATA_OUT ? true : false; in udc_ctrl_stage_is_data_out()
968 return data->stage == CTRL_PIPE_STAGE_DATA_IN ? true : false; in udc_ctrl_stage_is_data_in()
975 return data->stage == CTRL_PIPE_STAGE_STATUS_OUT ? true : false; in udc_ctrl_stage_is_status_out()
982 return data->stage == CTRL_PIPE_STAGE_STATUS_IN ? true : false; in udc_ctrl_stage_is_status_in()
989 return data->stage == CTRL_PIPE_STAGE_NO_DATA ? true : false; in udc_ctrl_stage_is_no_data()
1015 if (data->stage != CTRL_PIPE_STAGE_SETUP) { in udc_ctrl_update_stage()
1016 LOG_INF("Sequence %u not completed", data->stage); in udc_ctrl_update_stage()
1017 data->stage = CTRL_PIPE_STAGE_SETUP; in udc_ctrl_update_stage()
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| D | udc_nrf.c | 45 /* Let controller perform status stage */
130 /* Status stage finished, notify upper layer */ in udc_event_xfer_ctrl_in()
143 /* Update to next stage of control transfer */ in udc_event_xfer_ctrl_in()
218 /* Update to next stage of control transfer */ in udc_event_xfer_ctrl_out()
340 * switches to new address only after status stage. The device won't in udc_event_xfer_setup()
341 * automatically accept Data Stage packets. in udc_event_xfer_setup()
348 * * sends IN token (either incorrectly proceeds to status stage, or in udc_event_xfer_setup()
354 * a race condition between host issuing Set Address status stage (IN in udc_event_xfer_setup()
356 * ACKs status stage and use new address. If device wins the race, the in udc_event_xfer_setup()
357 * device STALLs status stage and address remains unchanged. in udc_event_xfer_setup()
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| D | udc_renesas_ra.c | 40 /* Let controller perform status stage */
164 /* Update to next stage of control transfer */ in udc_event_xfer_setup()
168 /* Allocate and feed buffer for data OUT stage */ in udc_event_xfer_setup()
186 /* Status stage finished, notify upper layer */ in udc_event_xfer_ctrl_in()
190 /* Update to next stage of control transfer */ in udc_event_xfer_ctrl_in()
194 /* IN transfer finished, perform status stage OUT and release buffer */ in udc_event_xfer_ctrl_in()
211 /* Perform status stage IN */ in udc_event_status_in()
223 /* Status stage finished, notify upper layer */ in udc_event_xfer_ctrl_out()
227 /* Update to next stage of control transfer */ in udc_event_xfer_ctrl_out()
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| /Zephyr-latest/subsys/usb/device/class/ |
| D | msc.c | 211 /* MSC Bulk-only Stage */
212 enum Stage { enum
221 static enum Stage stage; variable
272 stage = MSC_READ_CBW; in msd_state_machine_reset()
292 stage = MSC_WAIT_CSW; in sendCSW()
298 /* Stall data stage */ in fail()
319 stage = MSC_SEND_CSW; in write()
477 if (!length || (stage != MSC_PROCESS_CBW)) { in thread_memory_read_done()
478 csw.Status = (stage == MSC_PROCESS_CBW) ? in thread_memory_read_done()
480 stage = (stage == MSC_PROCESS_CBW) ? MSC_SEND_CSW : stage; in thread_memory_read_done()
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | vector_table_pad.ld | 8 * Padding inserted after the (first-stage) vector table, so that the
16 * first stage vector table.
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.xen | 36 console driver (HVC gets inited on PRE_KERNEL_1 stage).
43 Log output will become available on PRE_KERNEL_1 stage. Requires
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| /Zephyr-latest/drivers/usb/uhc/ |
| D | uhc_virtual.c | 99 if (xfer->stage == UHC_CONTROL_STAGE_SETUP) { in vrt_xfer_control()
100 LOG_DBG("Handle SETUP stage"); in vrt_xfer_control()
114 if (buf != NULL && xfer->stage == UHC_CONTROL_STAGE_DATA) { in vrt_xfer_control()
123 LOG_DBG("Handle DATA stage"); in vrt_xfer_control()
137 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in vrt_xfer_control()
140 LOG_DBG("Handle STATUS stage"); in vrt_xfer_control()
296 xfer->stage = UHC_CONTROL_STAGE_DATA; in vrt_hrslt_success()
298 xfer->stage = UHC_CONTROL_STAGE_STATUS; in vrt_hrslt_success()
303 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in vrt_hrslt_success()
304 LOG_DBG("Status stage finished"); in vrt_hrslt_success()
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| D | uhc_max3421e.c | 233 /* Force DATA1 PID for the data stage of control transfer */ in max3421e_tgl_next()
322 if (xfer->stage == UHC_CONTROL_STAGE_SETUP) { in max3421e_xfer_control()
323 LOG_DBG("Handle SETUP stage"); in max3421e_xfer_control()
338 if (buf != NULL && xfer->stage == UHC_CONTROL_STAGE_DATA) { in max3421e_xfer_control()
339 LOG_DBG("Handle DATA stage"); in max3421e_xfer_control()
343 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in max3421e_xfer_control()
344 LOG_DBG("Handle STATUS stage"); in max3421e_xfer_control()
452 xfer->stage = UHC_CONTROL_STAGE_DATA; in max3421e_hrslt_success()
454 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
477 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_opentitan.c | 70 * While the first stage supports an interrupt callback, the second does not.
71 * The second stage is mandatory to adjust the "bite" time window.
94 /* When multistage is selected, add an intermediate bark stage */ in ot_aontimer_install_timeout()
103 * Flag must be clear for stage 1, and reset SOC for stage 2. in ot_aontimer_install_timeout()
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| /Zephyr-latest/doc/build/cmake/ |
| D | index.rst | 8 CMake build is done in two stages. The first stage is called
16 **build** stage by executing the generated build scripts. These build scripts
163 :alt: Zephyr's build stage I
174 generated during the configuration phase and the pre-build stage(s)).
178 :alt: Zephyr's build stage II
208 :alt: Zephyr's build stage III
221 :alt: Zephyr's build stage IV
228 The binaries from the previous stage are incomplete, with empty and/or
294 The binary from the previous stage is incomplete, with empty and/or
297 The link from the previous stage is repeated, this time with the missing
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| /Zephyr-latest/soc/espressif/esp32s3/ |
| D | memory.h | 30 * The 2nd stage bootloader can take space up to the end of ROM shared
67 * This address is where 2nd stage bootloader starts allocating memory,
69 * When there is no 2nd stage bootloader the bootstrapping is done
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| /Zephyr-latest/dts/bindings/regulator/ |
| D | nordic,nrf53x-regulator-hv.yaml | 5 Nordic nRF53X regulator (high voltage stage of the main supply)
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| D | nordic,nrf52x-regulator-hv.yaml | 5 Nordic nRF52X regulator (high voltage stage of the main supply)
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| D | nordic,nrf5x-regulator.yaml | 5 Nordic nRF5X regulator (fixed stage of the core supply)
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc3.h | 43 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_NONE 0 /**< config without stage information */
44 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< config during hw_params stage */
45 #define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_FREE BIT(1) /**< config during hw_free stage */
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| /Zephyr-latest/boards/sparkfun/pro_micro_rp2040/ |
| D | sparkfun_pro_micro_rp2040.dts | 32 * the second stage bootloader
41 /* Reserved memory for the second stage bootloader */
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| /Zephyr-latest/soc/raspberrypi/rpi_pico/rp2040/ |
| D | linker.ld | 11 * The Second Stage Bootloader is only linked to the app that
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| /Zephyr-latest/tests/subsys/sensing/ |
| D | README.rst | 21 At the current stage, it only supports native_sim.
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| /Zephyr-latest/dts/bindings/clock/ |
| D | raspberrypi,pico-rosc.yaml | 22 stage-drive-strength:
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| /Zephyr-latest/doc/safety/ |
| D | safety_overview.rst | 155 Stage I (COMPLETED)
160 Stage II
169 Stage III
173 Stage IV
185 **Current stage:**
186 The prerequisites to complete **Stage II** are currently being looked at:
306 being certified. If the certification body approves everything at this stage and the safety
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| /Zephyr-latest/samples/subsys/sensing/simple/ |
| D | README.rst | 39 At the current stage, it only support native sim.
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| /Zephyr-latest/doc/connectivity/bluetooth/api/mesh/ |
| D | dfu.rst | 81 Upload stage
83 phone or gateway (the Initiator). During the Upload stage, the Initiator transfers the firmware
88 time-consuming Distribution stage. Once the firmware has been uploaded to the Distributor, the
89 Initiator may trigger the Distribution stage at any time.
91 Firmware Capability Check stage (optional)
92 Before starting the Distribution stage, the Initiator may optionally check if Target nodes can
96 Distribution stage
235 The Initiator controls the Upload stage of the DFU protocol, and all Distributor side handling of
238 The Distribution stage is controlled by the Distributor, as implemented by the
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| /Zephyr-latest/doc/services/debugging/ |
| D | symtab.rst | 7 stage that keep tracks of the information about the functions' name and address, for advanced appli…
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| /Zephyr-latest/cmake/ |
| D | yaml-filter.cmake | 4 # Simple second stage filter for YAML generation, used when generator
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