| /Zephyr-latest/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 1 description: ESP32 SPI
3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
26 description: Enable dummy SPI compensation cycles
31 Enable 3-wire mode
[all …]
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| D | microchip,xec-qmspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-qmspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 description: SPI Port 0 or 1.
19 pinctrl-0:
22 pinctrl-names:
48 description: Delay in system clocks from CS# assertion to first clock edge
53 description: Delay in system clocks from last clock edge to CS# de-assertion
58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
63 description: Delay in system clocks from CS# de-assertion to CS# assertion
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| D | microchip,xec-qmspi-ldma.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
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| D | spi-device.yaml | 1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for SPI devices
8 on-bus: spi
13 spi-max-frequency:
16 description: Maximum clock frequency of device's SPI interface in Hz
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
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| /Zephyr-latest/boards/shields/x_nucleo_bnrg2a1/ |
| D | x_nucleo_bnrg2a1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,bt-hci = &hci_spi;
14 cs-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; /* A1 */
16 hci_spi: bluenrg-2@0 {
17 compatible = "st,hci-spi-v2";
19 reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
20 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
21 spi-cpha; /* CPHA=1 */
22 spi-hold-cs;
23 spi-max-frequency = <DT_FREQ_M(1)>;
[all …]
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| /Zephyr-latest/boards/shields/x_nucleo_idb05a1/ |
| D | x_nucleo_idb05a1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,bt-hci = &spbtle_rf_x_nucleo_idb05a1;
14 cs-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; /* A1 */
16 spbtle_rf_x_nucleo_idb05a1: spbtle-rf@0 {
17 compatible = "st,hci-spi-v1";
19 reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
20 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
21 spi-max-frequency = <DT_FREQ_M(2)>;
22 spi-hold-cs;
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| /Zephyr-latest/boards/shields/x_nucleo_wb05kn1/ |
| D | x_nucleo_wb05kn1_spi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,bt-hci = &hci_spi;
14 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
17 compatible = "st,hci-spi-v2";
19 reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
20 irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */
21 spi-cpol; /* CPOL=1 */
22 spi-cpha; /* CPHA=1 */
23 spi-hold-cs;
24 spi-max-frequency = <DT_FREQ_M(8)>; /* the maximum supported SPI speed */
[all …]
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | nxp,imx-flexspi-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
20 cs-interval:
28 cs-setup-time:
36 cs-hold-time:
40 Chip select hold time, in serial clock cycles. See the TCSH field in
44 data-valid-time:
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| /Zephyr-latest/tests/drivers/flash/common/boards/ |
| D | nrf52840dk_spi_nor_wp_hold.overlay | 4 * SPDX-License-Identifier: Apache-2.0
6 * Build test for jedec,spi-nor compatible (drivers/flash/spi_nor.c) wp-gpios and hold-gpios
9 /delete-node/ &mx25r64;
25 low-power-enable;
31 compatible = "nordic,nrf-spim";
33 cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; // mx25v16
34 pinctrl-0 = <&spi0_default>;
35 pinctrl-1 = <&spi0_sleep>;
36 pinctrl-names = "default", "sleep";
39 compatible = "jedec,spi-nor";
[all …]
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
26 mipi-cpha:
29 SPI clock phase that indicates on which edge data is sampled.
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| /Zephyr-latest/samples/drivers/jesd216/boards/ |
| D | nrf52840dk_nrf52840_spi.overlay | 2 * Copyright (c) 2022-2023 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &mx25r64;
14 * to provide quad-spi feature. In individual specifications each of the spi
21 compatible = "nordic,nrf-spi";
23 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
24 pinctrl-0 = <&spi2_default>;
25 pinctrl-1 = <&spi2_sleep>;
26 pinctrl-names = "default", "sleep";
28 compatible = "jedec,spi-nor";
[all …]
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| /Zephyr-latest/boards/nxp/mimxrt1050_evk/ |
| D | mimxrt1050_evk_mimxrt1052_hyperflash.dts | 4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 pinctrl-0 = <&pinmux_flexspi1>;
22 pinctrl-names = "default";
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
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| /Zephyr-latest/boards/nxp/mimxrt1060_evk/ |
| D | mimxrt1060_evk_mimxrt1062_hyperflash.dts | 4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 ahb-bufferable;
22 ahb-cacheable;
23 sck-differential-clock;
24 combination-mode;
25 rx-clock-source = <3>;
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| /Zephyr-latest/dts/bindings/net/wireless/ |
| D | nordic,nrf21540-fem.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 This is a representation of the nRF21540 Radio Front-End module.
8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
9 interface. The SPI interface should be configured as a child node
10 of the SPI bus you have connected to the FEM. Then you "connect"
11 the FEM and SPI configurations using the spi-if property.
13 Here is an example nRF21540 configuration with a SPI interface
17 compatible = "nordic,nrf-spim";
19 cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
22 my_spi_if: nrf21540-spi@0 {
[all …]
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| /Zephyr-latest/boards/st/sensortile_box/ |
| D | sensortile_box.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/l4/stm32l4r9z(g-i)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,sensortile-box";
18 zephyr,shell-uart = &usart1;
21 zephyr,bt-c2h-uart = &usart1;
22 zephyr,bt-hci = &spbtle_1s_sensortile_box;
26 compatible = "gpio-leds";
39 compatible = "gpio-keys";
[all …]
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| /Zephyr-latest/boards/nxp/frdm_rw612/ |
| D | frdm_rw612_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_rw612-pinctrl.dtsi"
15 usart-0 = &flexcomm3;
16 i2c-0 = &flexcomm2;
17 pwm-0 = &sctimer;
24 zephyr,shell-uart = &flexcomm3;
28 compatible = "gpio-leds";
36 compatible = "nxp,lpc-usart";
38 current-speed = <115200>;
39 pinctrl-0 = <&pinmux_flexcomm3_usart>;
[all …]
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| /Zephyr-latest/boards/ezurio/bl654_dvk/ |
| D | bl654_dvk.dts | 6 * SPDX-License-Identifier: Apache-2.0
9 /dts-v1/;
12 #include "bl654_dvk-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
21 zephyr,shell-uart = &uart0;
22 zephyr,uart-mcumgr = &uart0;
23 zephyr,bt-mon-uart = &uart0;
24 zephyr,bt-c2h-uart = &uart0;
29 compatible = "gpio-leds";
49 compatible = "gpio-keys";
[all …]
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | spi.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for SPI drivers and applications
16 * @brief SPI Interface
17 * @defgroup spi_interface SPI Interface
27 #include <zephyr/dt-bindings/spi/spi.h>
39 * @name SPI operational mode
47 /** Get SPI operational mode. */
52 * @name SPI Polarity & Phase Modes
73 * Whatever data is transmitted is looped-back to the receiving buffer of
81 /** Get SPI polarity and phase mode bits. */
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| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_spi.c | 6 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/drivers/spi.h>
24 #include <zephyr/dt-bindings/led/led.h>
26 /* spi-one-frame and spi-zero-frame in DT are for 8-bit frames. */
30 * SPI master configuration:
32 * - mode 0 (the default), 8 bit, MSB first (arbitrary), one-line SPI
33 * - no shenanigans (don't hold CS, don't hold the device lock, this
52 return dev->config; in dev_cfg()
56 * Serialize an 8-bit color channel value into an equivalent sequence
57 * of SPI frames, MSbit first, where a one bit becomes SPI frame
[all …]
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| D | lpd880x.c | 4 * SPDX-License-Identifier: Apache-2.0
24 #include <zephyr/drivers/spi.h>
28 * LPD880X SPI master configuration:
30 * - mode 0 (the default), 8 bit, MSB first, one-line SPI
31 * - no shenanigans (no CS hold, release device lock, not an EEPROM)
44 const struct lpd880x_config *config = dev->config; in lpd880x_update()
79 rc = spi_write_dt(&config->bus, &tx); in lpd880x_update()
96 * Overwrite a prefix of the pixels array with its on-wire in lpd880x_strip_update_rgb()
131 const struct lpd880x_config *config = dev->config; in lpd880x_strip_length()
133 return config->length; in lpd880x_strip_length()
[all …]
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| /Zephyr-latest/tests/boards/mec172xevb_assy6906/qspi/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/spi.h>
29 /* bits[7:0] = spi opcode,
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
77 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready"); in spi_single_init()
87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
[all …]
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| /Zephyr-latest/include/zephyr/mgmt/ec_host_cmd/ |
| D | backend.h | 4 * SPDX-License-Identifier: Apache-2.0
44 * Buffer to hold received data. The buffer is provided by the handler if
150 * @brief Get the SPI Host Command backend pointer
152 * Get the SPI pointer backend and pass a chip select pin that will be used for the Host Command
155 * @param cs Chip select pin..
157 * @retval The SPI backend pointer.
159 struct ec_host_cmd_backend *ec_host_cmd_backend_get_spi(struct gpio_dt_spec *cs);
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| /Zephyr-latest/boards/st/b_l4s5i_iot01a/ |
| D | b_l4s5i_iot01a.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/l4/stm32l4s5vitx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics B-L4S5I-IOT01A discovery kit";
15 compatible = "st,b-l4s5i-iot01a";
19 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
23 zephyr,flash-controller = &mx25r6435f;
24 zephyr,bt-c2h-uart = &usart1;
[all …]
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| /Zephyr-latest/boards/st/steval_stwinbx1/ |
| D | steval_stwinbx1.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics STEVAL-STWINBX1 Development kit";
19 zephyr,code-partition = &slot0_partition;
21 zephyr,bt-hci = &hci_spi;
25 compatible = "gpio-leds";
37 compatible = "pwm-leds";
41 label = "LED_1 - PWM5";
[all …]
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| /Zephyr-latest/boards/st/sensortile_box_pro/ |
| D | sensortile_box_pro.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics SENSORTILE-BOX-PRO board";
14 compatible = "st,sensortile-box-pro";
19 zephyr,code-partition = &slot0_partition;
20 zephyr,bt-hci = &hci_spi;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
[all …]
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