| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | litex,clkout.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
18 Typically 0 for nodes with a single clock output
22 clock-output-names:
28 litex,clock-frequency:
34 litex,clock-phase:
38 default phase offset given in degrees
40 litex,clock-duty-num:
46 litex,clock-duty-den:
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| /Zephyr-Core-3.5.0/dts/bindings/qspi/ |
| D | nxp,s32-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
32 Selects the read mode:
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
30 duty-cycle = <32768>;
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| /Zephyr-Core-3.5.0/samples/drivers/clock_control_litex/ |
| D | README.rst | 1 .. zephyr:code-sample:: clock-control-litex
3 :relevant-api: clock_control_interface
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
24 :start-at: clk0: clock-controller@0 {
25 :end-at: };
27 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
28 :start-at: clk1: clock-controller@1 {
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | nxp,mcux-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-qdec"
8 include: [pinctrl-device.yaml, sensor-device.yaml]
17 counts-per-revolution:
24 single-phase-mode:
31 filter-count:
39 filter-sample-period:
|
| /Zephyr-Core-3.5.0/include/zephyr/bluetooth/mesh/ |
| D | blob.h | 4 * SPDX-License-Identifier: Apache-2.0
28 /** BLOB transfer mode. */
30 /** No valid transfer mode. */
32 /** Push mode (Push BLOB Transfer Mode). */
34 /** Pull mode (Pull BLOB Transfer Mode). */
40 /** Transfer phase. */
75 * phase.
85 /** The transfer mode is not supported by the BLOB Transfer Server
92 * the current phase.
128 /** BLOB transfer mode. */
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| D | blob_srv.h | 4 * SPDX-License-Identifier: Apache-2.0
27 * @brief Max number of blocks in a single transfer.
140 enum bt_mesh_blob_xfer_phase phase; member
154 /* Pull mode (Pull BLOB Transfer Mode) behavior. */
172 * base 10 seconds, in 10-second increments.
|
| /Zephyr-Core-3.5.0/tests/bsim/bluetooth/mesh/src/ |
| D | test_blob.c | 4 * SPDX-License-Identifier: Apache-2.0
39 .option = "use-pull-mode", in test_args_parse()
40 .descript = "Set transfer type to pull mode" in test_args_parse()
46 .option = "msg-fail-type", in test_args_parse()
52 .name = "{inactive, start, wait-block, wait-chunk, complete, suspended}", in test_args_parse()
53 .option = "expected-phase", in test_args_parse()
54 .descript = "Expected DFU Server phase value restored from flash" in test_args_parse()
63 enum bt_mesh_blob_io_mode mode) in blob_io_open() argument
79 partial_block += chunk->size; in blob_chunk_wr()
80 ASSERT_TRUE_MSG(partial_block <= block->size, "Received block is too large\n"); in blob_chunk_wr()
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| /Zephyr-Core-3.5.0/doc/hardware/peripherals/canbus/ |
| D | controller.rst | 13 Controller Area Network is a two-wire serial bus specified by the
14 Bosch CAN Specification, Bosch CAN with Flexible Data-Rate specification and the
15 ISO 11898-1:2003 standard.
20 from the CAN controller to the bus-levels. The bus lines are called
24 These wires use the logic levels whereas the bus-level is interpreted
29 To write a dominant bit to the bus, open-drain transistors tie CAN H to Vdd
31 The first and last node use a 120-ohm resistor between CAN H and CAN L to
33 This structure is called a wired-AND.
40 loopback mode.
48 The bit-timing as defined in ISO 11898-1:2003 looks as following:
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| /Zephyr-Core-3.5.0/tests/boards/mec172xevb_assy6906/qspi/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
93 static uint32_t spi_clocks_to_bytes(uint32_t spi_clocks, uint8_t mode) in spi_clocks_to_bytes() argument
97 if (mode == 4u) { in spi_clocks_to_bytes()
99 } else if (mode == 2u) { in spi_clocks_to_bytes()
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_xlnx_axi_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
39 /* Generate PWM mode, count-down, auto-reload */
51 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_read32()
53 return sys_read32(config->base + offset); in xlnx_axi_timer_read32()
60 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_write32()
62 sys_write32(value, config->base + offset); in xlnx_axi_timer_write32()
69 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_set_cycles()
76 return -ENOTSUP; in xlnx_axi_timer_set_cycles()
102 return -ENOTSUP; in xlnx_axi_timer_set_cycles()
106 tlr0 = period_cycles - 2; in xlnx_axi_timer_set_cycles()
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_sifive.c | 4 * SPDX-License-Identifier: Apache-2.0
38 return -ENOTSUP; in spi_config()
42 return -ENOTSUP; in spi_config()
46 return -ENOTSUP; in spi_config()
50 div = (SPI_CFG(dev)->f_sys / (frequency * 2U)) - 1; in spi_config()
62 /* Set the phase */ in spi_config()
77 return -ENOTSUP; in spi_config()
87 return -ENOTSUP; in spi_config()
89 /* Set single line operation */ in spi_config()
129 struct spi_context *ctx = &SPI_DATA(dev)->ctx; in spi_sifive_xfer()
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ke1xf/ |
| D | soc.c | 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
121 /* System Phase-Locked Loop (SPLL) configuration */
144 .prediv = (SCG_CLOCK_DIV(pll) - 1U),
145 .mult = (SCG_CLOCK_MULT(pll) - 16U)
176 /* Only RUN mode supported for now */ in clk_init()
250 * Note that the KE1xF does not implement the optional ARMv7-M memory in ke1xf_init()
252 * Cortex-M4 core. Instead, the processor includes its own MPU module. in ke1xf_init()
254 temp_reg = SYSMPU->CESR; in ke1xf_init()
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | spi.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #include <zephyr/dt-bindings/spi/spi.h>
37 * @name SPI operational mode
47 * @name SPI Polarity & Phase Modes
59 * Clock Phase: this dictates when is the data captured, and depends
68 * Whatever data is transmitted is looped-back to the receiving buffer of
105 /* Requests - if possible - to keep CS asserted after the transaction */
114 /* Active high logic on CS - Usually, and by default, CS logic is active
129 * Default is single, which is the case most of the time.
130 * Without @kconfig{CONFIG_SPI_EXTENDED_MODES} being enabled, single is the
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| /Zephyr-Core-3.5.0/include/zephyr/net/ |
| D | ieee802154_radio.h | 5 * SPDX-License-Identifier: Apache-2.0
12 * @note All references to the standard in this file cite IEEE 802.15.4-2020.
35 * @details This API provides a common representation of vendor-specific
41 * - a basic, mostly PHY-level driver API to be implemented by all drivers,
42 * - several optional MAC-level extension points to offload performance
48 * offloading to vendor-specific hardware or firmware features may be required
53 * Whether or not MAC-level offloading extension points need to be implemented
57 * @note All section, table and figure references are to the IEEE 802.15.4-2020
64 * @name IEEE 802.15.4-2020, Section 6: MAC functional description
87 * @name IEEE 802.15.4-2020, Section 8: MAC services
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| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-3.5.rst | 38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
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| D | release-notes-1.7.rst | 10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
32 spirit in that it allows a single thread to monitor multiple events without
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
102 * Created net-shell module for interacting with network sub-system.
114 * Utilized new k_poll API to consolidate all TX threads into a single one
136 * Imported Segger J-Link RTT library
145 * New local-content generation theme (read-the-docs)
147 * Site-wide glossary added.
150 * Improved consistency of :ref:`boards` and :ref:`samples-and-demos`.
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| D | release-notes-2.5.rst | 27 * CVE-2021-3323: Under embargo until 2021-04-14
28 * CVE-2021-3321: Under embargo until 2021-04-14
29 * CVE-2021-3320: Under embargo until 2021-04-14
39 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
56 * Changed vcnl4040 dts binding default for property 'proximity-trigger'.
63 * The :c:func:`mqtt_keepalive_time_left` function now returns -1 if keep alive
66 * The ``CONFIG_LEGACY_TIMEOUT_API`` mode has been removed. All kernel
67 timeout usage must use the new-style k_timeout_t type and not the
87 GPIO-only regulators a devicetree property ``supply-gpios`` is defined as a
101 * ARM Musca-A board and SoC support deprecated and planned to be removed in 2.6.0.
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| D | release-notes-3.1.rst | 32 * Disk Subsystem: SPI mode SD cards now use the SD subsystem to communicate
61 * Split CAN classic and CAN-FD APIs:
68 * Converted the ``enum can_mode`` into a ``can_mode_t`` bitfield and renamed the CAN mode
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/api/mesh/ |
| D | shell.rst | 29 The Bluetooth mesh shell subsystem adds a single ``mesh`` command, which holds a set of
30 sub-commands. Every time the device boots up, make sure to call ``mesh init`` before any of the
43 The simplest way to provision the device is through self-provisioning. To do this the user must
49 devices, as long as they're assigned non-overlapping unicast addresses. Alternatively, to provision
51 ``mesh prov pb-adv on`` or ``mesh prov pb-gatt on``. The beacons can be picked up by an external
68 ``mesh prov local`` command above), we can perform self-configuration through any of the
73 uart:~$ mesh models cfg get-comp
89 uart:~$ mesh test net-send 82020100
120 .. list-table:: Parameter formats
122 :header-rows: 1
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| /Zephyr-Core-3.5.0/drivers/flash/ |
| D | spi_nor.c | 2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
34 * * When CSn is deasserted the device enters a standby mode.
35 * * Some devices support a Deep Power-Down mode which reduces current
46 * deep-power-down mode.
73 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
75 /* Build-time data associated with the device. */
95 /* Expected JEDEC ID, from jedec-id property */
99 /* Optional support for entering 32-bit address mode. */
104 /* Length of BFP structure, in 32-bit words. */
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| D | flash_stm32_ospi.c | 5 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/flash_controller/ospi.h>
181 struct flash_stm32_ospi_data *dev_data = dev->data; in ospi_lock_thread()
183 k_sem_take(&dev_data->sem, K_FOREVER); in ospi_lock_thread()
188 struct flash_stm32_ospi_data *dev_data = dev->data; in ospi_unlock_thread()
190 k_sem_give(&dev_data->sem); in ospi_unlock_thread()
195 const struct flash_stm32_ospi_config *dev_cfg = dev->config; in ospi_send_cmd()
196 struct flash_stm32_ospi_data *dev_data = dev->data; in ospi_send_cmd()
199 LOG_DBG("Instruction 0x%x", cmd->Instruction); in ospi_send_cmd()
201 dev_data->cmd_status = 0; in ospi_send_cmd()
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| D | flash_andes_qspi.c | 4 * SPDX-License-Identifier: Apache-2.0
93 const struct flash_andes_qspi_data *dev_data = dev->data; in dev_erase_types()
95 return dev_data->erase_types; in dev_erase_types()
102 const struct flash_andes_qspi_data *dev_data = dev->data; in dev_flash_size()
104 return dev_data->flash_size; in dev_flash_size()
106 const struct flash_andes_qspi_config *config = dev->config; in dev_flash_size()
108 return config->flash_size; in dev_flash_size()
115 const struct flash_andes_qspi_data *dev_data = dev->data; in dev_page_size()
117 return dev_data->page_size; in dev_page_size()
135 struct flash_andes_qspi_data *dev_data = dev->data; in flash_andes_qspi_access()
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| /Zephyr-Core-3.5.0/doc/services/logging/ |
| D | index.rst | 17 - Deferred logging reduces the time needed to log a message by shifting time
20 - Multiple backends supported (up to 9 backends).
21 - Custom frontend support. It can work together with backends.
22 - Compile time filtering on module level.
23 - Run time filtering independent for each backend.
24 - Additional run time filtering on module instance level.
25 - Timestamping with user provided function. Timestamp can have 32 or 64 bits.
26 - Dedicated API for dumping data.
27 - Dedicated API for handling transient strings.
28 - Panic support - in panic mode logging switches to blocking, synchronous
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| /Zephyr-Core-3.5.0/boards/xtensa/esp32_ethernet_kit/doc/ |
| D | index.rst | 3 ESP32-ETHERNET-KIT
6 The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables
7 Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide
8 more flexible power supply options, the ESP32-Ethernet-Kit also supports power
11 .. _get-started-esp32-ethernet-kit-v1.2-overview:
13 .. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg
15 :alt: ESP32-Ethernet-Kit V1.2
16 :figclass: align-center
18 ESP32-Ethernet-Kit V1.2 Overview
23 ESP32-Ethernet-Kit is an ESP32-based development board produced by
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|
