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/Zephyr-latest/drivers/disk/
DKconfig.sdmmc8 bool "SDMMC card driver"
13 SDMMC card driver.
21 SDMMC controller driver initialization priority.
24 bool "SDMMC access via SD subsystem"
29 Enable SDMMC access via SD subsystem.
32 bool "STM32 SDMMC driver"
45 File system on sdmmc accessed through stm32 sdmmc.
48 bool "STM32 SDMMC Hardware Flow control"
56 Enable SDMMC Hardware Flow Control to avoid FIFO underrun (TX mode) and
60 bool "STM32 SDMMC eMMC mode"
[all …]
DKconfig13 source "drivers/disk/Kconfig.sdmmc"
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_sdmmc.c40 zassert_true((r == 0), "Could not enable SDMMC gating clock"); in ZTEST()
42 zassert_true(__HAL_RCC_SDIO_IS_CLK_ENABLED(), "SDMMC gating clock should be on"); in ZTEST()
43 TC_PRINT("SDMMC gating clock on\n"); in ZTEST()
60 zassert_true((r == 0), "Could not enable SDMMC domain clock"); in ZTEST()
61 TC_PRINT("SDMMC domain clock configured\n"); in ZTEST()
68 "Expected SDMMC src: CLK 48 (0x%lx). Actual src: 0x%x", in ZTEST()
72 "Expected SDMMC src: SYSCLK (0x%lx). Actual src: 0x%x", in ZTEST()
84 TC_PRINT("SDMMC sourced by PLLQ at "); in ZTEST()
97 TC_PRINT("SDMMC sourced by PLLI2SQ at "); in ZTEST()
110 zassert_true((r == 0), "Could not get SDMMC clk srce freq"); in ZTEST()
[all …]
/Zephyr-latest/dts/bindings/mmc/
Dst,stm32-sdmmc.yaml1 description: stm32 sdmmc disk access
3 compatible: "st,stm32-sdmmc"
35 bus width for SDMMC access, defaults to the minimum necessary
46 Clock division factor for SDMMC. Typically the clock operates at 25MHz so
52 SDMMC device has an internal DMA. Internal DMA doesn't require any additional
65 For example dmas for TX/RX on SDMMC
/Zephyr-latest/dts/bindings/sd/
Dzephyr,sdmmc-disk.yaml2 Zephyr SDMMC disk node. A binding with this compatible present within an SD
3 host controller device node indicates that an SDMMC disk is attached to that
7 compatible: "zephyr,sdmmc-disk"
/Zephyr-latest/boards/shields/pmod_sd/
Dpmod_sd.overlay16 sdmmc {
17 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/tests/drivers/build_all/disk/
Dspi.dtsi12 sdmmc {
13 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/dts/arm/st/h5/
Dstm32h563.dtsi13 sdmmc2: sdmmc@46008c00 {
14 compatible = "st,stm32-sdmmc";
/Zephyr-latest/tests/subsys/fs/fat_fs_api/
Dtestcase.yaml18 filesystem.fat.api.sdmmc:
20 filter: dt_compat_enabled("zephyr,sdmmc-disk")
/Zephyr-latest/boards/shields/adafruit_adalogger_featherwing/
Dadafruit_adalogger_featherwing.overlay24 sdmmc {
25 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/tests/subsys/sd/sdmmc/
DREADME.txt1 SDMMC Subsystem Test
13 test the initialization flow of the SDMMC subsystem to verify that the stack
Dtestcase.yaml7 sd.sdmmc:
/Zephyr-latest/boards/intel/socfpga/agilex5_socdk/
Dintel_socfpga_agilex5_socdk.dts24 &sdmmc {
28 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/boards/shields/adafruit_data_logger/
Dadafruit_data_logger.overlay44 sdmmc {
45 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi35 sdmmc2: sdmmc@40011c00 {
36 compatible = "st,stm32-sdmmc";
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dintel_socfpga_agilex5_socdk.overlay7 &sdmmc {
Dhifive_unmatched.overlay15 compatible = "zephyr,sdmmc-disk";
/Zephyr-latest/subsys/sd/
DCMakeLists.txt8 zephyr_library_sources_ifdef(CONFIG_SDMMC_STACK sdmmc.c)
DKconfig14 bool "SDMMC protocol support"
16 Enable SDMMC protocol support. Required for SD memory cards to
/Zephyr-latest/boards/st/stm32u5a9j_dk/
Dstm32u5a9j_dk.yaml20 - sdmmc
/Zephyr-latest/tests/subsys/fs/ext2/boards/
Dek_ra8d1.overlay7 sdmmc {
Dek_ra8m1.overlay7 sdmmc {
Dmck_ra8t1.overlay7 sdmmc {
Dhifive_unmatched_fu740_s7.overlay15 compatible = "zephyr,sdmmc-disk";
Dhifive_unmatched_fu740_u74.overlay15 compatible = "zephyr,sdmmc-disk";

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