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/Zephyr-latest/dts/bindings/mbox/
Dnordic,mbox-nrf-ipc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,mbox-nrf-ipc"
8 include: [base.yaml, mailbox-controller.yaml]
11 tx-mask:
14 description: TX supported channels mask
16 rx-mask:
19 description: RX supported channels mask
24 mbox-cells:
25 - channel
Dnordic,nrf-vevif-event-rx.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic VEVIF (VPR Event Interface) - EVENT RX MODE
7 VEVIF provides support for inter-domain software signaling. It implements a set of events
9 When used in the event rx mode, the VEVIF events are used to receive IRQs that are
17 compatible = "nordic,nrf-vevif-event-rx";
20 #mbox-cells = <1>;
22 nordic,events-mask = <0x00008000>;
26 compatible: "nordic,nrf-vevif-event-rx"
28 include: [base.yaml, mailbox-controller.yaml]
36 nordic,events-mask:
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Dnordic,nrf-vevif-task-rx.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic VEVIF (VPR Event Interface) - TASK RX MODE
10 VEVIF provides support for inter-domain software signaling. It implements a set of tasks
12 When used in task rx mode, the VEVIF tasks are used to receive events triggered by other core.
19 compatible = "nordic,nrf-vevif-task-rx";
24 #mbox-cells = <1>;
26 nordic,tasks-mask = <0xfffffff0>;
30 compatible: "nordic,nrf-vevif-task-rx"
32 include: [base.yaml, mailbox-controller.yaml]
40 nordic,tasks-mask:
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/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
11 /* 10 Mbit/s transfer with full duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
15 /* 100 Mbit/s transfer with full duplex mask. */
38 /* Speed and duplex mode staus mask. */
40 /* Link status mask. */
53 /* Address Table Command Result flag mask */
78 /* Port number or port map mask*/
114 /* Interrupt Mask & Control Register PHY Address. */
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_rf2xx_iface.c1 /* ieee802154_rf2xx_iface.c - ATMEL RF2XX IEEE 802.15.4 Interface */
4 * Copyright (c) 2019-2020 Gerson Fernando Budke
6 * SPDX-License-Identifier: Apache-2.0
29 const struct rf2xx_config *conf = dev->config; in rf2xx_iface_phy_rst()
32 gpio_pin_set_dt(&conf->reset_gpio, 0); in rf2xx_iface_phy_rst()
33 gpio_pin_set_dt(&conf->slptr_gpio, 0); in rf2xx_iface_phy_rst()
38 gpio_pin_set_dt(&conf->reset_gpio, 1); in rf2xx_iface_phy_rst()
40 gpio_pin_set_dt(&conf->reset_gpio, 0); in rf2xx_iface_phy_rst()
44 const struct rf2xx_config *conf = dev->config; in rf2xx_iface_phy_tx_start()
47 gpio_pin_set_dt(&conf->slptr_gpio, 1); in rf2xx_iface_phy_tx_start()
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Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
69 /* Access mask to SYS_CFG_ID */
75 /* Frame Filtering Behave as a Co-ordinator */
97 /* Disable Double RX Buffer */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
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/Zephyr-latest/drivers/ipm/
Dipm_stm32_ipcc.c4 * SPDX-License-Identifier: Apache-2.0
24 ((const struct stm32_ipcc_mailbox_config * const)(dev)->config)->uconf.base)
53 #define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C1##reg)
55 #define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
56 #define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
81 #define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C2##reg)
83 #define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
84 #define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
104 struct stm32_ipcc_mbx_data *data = dev->data; in stm32_ipcc_mailbox_rx_isr()
105 const struct stm32_ipcc_mailbox_config *cfg = dev->config; in stm32_ipcc_mailbox_rx_isr()
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/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
50 #define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
53 #define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
54 #define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
62 #define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
67 #define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
70 #define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
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Duart_mcux_flexcomm.c2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
114 USART_WriteByte(config->base, c); in mcux_flexcomm_poll_out()
119 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_err_check()
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Duart_mcux_lpuart.c2 * Copyright 2017,2021,2023-2024 NXP
5 * SPDX-License-Identifier: Apache-2.0
133 struct mcux_lpuart_data *data = dev->data; in mcux_lpuart_pm_policy_state_lock_get()
135 if (!data->pm_state_lock_on) { in mcux_lpuart_pm_policy_state_lock_get()
136 data->pm_state_lock_on = true; in mcux_lpuart_pm_policy_state_lock_get()
143 struct mcux_lpuart_data *data = dev->data; in mcux_lpuart_pm_policy_state_lock_put()
145 if (data->pm_state_lock_on) { in mcux_lpuart_pm_policy_state_lock_put()
146 data->pm_state_lock_on = false; in mcux_lpuart_pm_policy_state_lock_put()
154 const struct mcux_lpuart_config *config = dev->config; in mcux_lpuart_poll_in()
155 uint32_t flags = LPUART_GetStatusFlags(config->base); in mcux_lpuart_poll_in()
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/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_spi.c4 * SPDX-License-Identifier: Apache-2.0
58 const struct spi_buf_set rx = { in spi_read_register() local
63 return spi_transceive_dt(bus, &tx, &rx); in spi_read_register()
76 int icm42688_spi_update_register(const struct spi_dt_spec *bus, uint16_t reg, uint8_t mask, in icm42688_spi_update_register() argument
86 temp &= ~mask; in icm42688_spi_update_register()
87 temp |= FIELD_PREP(mask, data); in icm42688_spi_update_register()
/Zephyr-latest/drivers/ethernet/
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
77 /* Port 2 RX FIFO Contains Data */
81 /* Port 1 RX FIFO Contains Data */
90 /* Rx chunks available */
96 /* Interrupt Mask Register 0 */
98 /* Physical Layer Interrupt Mask */
101 /* Interrupt Mask Register 1 */
103 /* Mask Bit for P2_PHYINT */
105 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/
107 /*!< Mask Bit for SPI_ERR. Generic SPI only. */
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/Zephyr-latest/subsys/canbus/isotp/
DKconfig1 # ISO-TP configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ISO-TP Transport [EXPERIMENTAL]"
18 module-str = ISOTP
34 Timeout for the reception of the next FC frame. ISO 15765-2: 1000ms
42 ISO 15765-2: 1000ms
50 ISO 15765-2: 1000ms
83 CAN_MAX_DLEN - 1 (for classic CAN : 8 - 1 = 7, for CAN FD : 64 - 1 = 63).
92 Each buffer will occupy CAN_MAX_DLEN - 1 byte + header (sizeof(struct net_buf))
140 If not set ISO-TP fixed addressing use SAE J1939 standard.
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
28 /** Mask for the function field. */
33 /** Mask for the pin field. */
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/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl_spi.c1 /* lsm6dsl_spi.c - SPI routines for LSM6DSL driver
7 * SPDX-License-Identifier: Apache-2.0
26 const struct lsm6dsl_config *cfg = dev->config; in lsm6dsl_raw_read()
46 const struct spi_buf_set rx = { in lsm6dsl_raw_read() local
53 return -EIO; in lsm6dsl_raw_read()
56 if (spi_transceive_dt(&cfg->bus_cfg.spi, &tx, &rx)) { in lsm6dsl_raw_read()
57 return -EIO; in lsm6dsl_raw_read()
66 const struct lsm6dsl_config *cfg = dev->config; in lsm6dsl_raw_write()
85 return -EIO; in lsm6dsl_raw_write()
88 if (spi_write_dt(&cfg->bus_cfg.spi, &tx)) { in lsm6dsl_raw_write()
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/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
61 /* used to fetch the word width. If the "word-width" property is not specified,
76 #define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4))
88 ((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f))
94 #define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4)
96 #define _ESAI_RX_FIFO_USAGE_EN(mask)\ argument
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/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372_spi.c1 /* adxl372_spi.c - SPI routines for ADXL372 driver
7 * SPDX-License-Identifier: Apache-2.0
24 const struct adxl372_dev_config *config = dev->config; in adxl372_bus_access()
41 const struct spi_buf_set rx = { in adxl372_bus_access() local
48 return spi_transceive_dt(&config->spi, &tx, &rx); in adxl372_bus_access()
53 return spi_write_dt(&config->spi, &tx); in adxl372_bus_access()
81 uint32_t mask, in adxl372_spi_reg_write_mask() argument
92 tmp &= ~mask; in adxl372_spi_reg_write_mask()
107 struct adxl372_data *data = dev->data; in adxl372_spi_init()
108 const struct adxl372_dev_config *config = dev->config; in adxl372_spi_init()
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/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_stm32_priv.h4 * SPDX-License-Identifier: Apache-2.0
17 * @brief The packet type(SOP*) consists of 2-bytes
22 * @brief The message header consists of 2-bytes
34 * @brief UCPD alert mask used for enabling alerts
43 * @brief UCPD alert mask used for clearing alerts
52 * @brief UCPD alert mask used for enabling alerts
62 * @brief UCPD alert mask used for clearing alerts
71 * @brief UCPD alert mask for all alerts
98 #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
194 TX_MSG_NONE = -1,
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/Zephyr-latest/dts/riscv/nordic/
Dnrf54l_05_10_15_cpuflpr.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 /delete-node/ &cpuapp;
11 /delete-node/ &cpuapp_rram;
12 /delete-node/ &cpuapp_ppb;
13 /delete-node/ &cpuapp_sram;
17 compatible = "simple-bus";
18 interrupt-parent = <&cpuflpr_clic>;
25 compatible = "nordic,nrf-vevif-task-rx";
27 interrupt-parent = <&cpuflpr_clic>;
35 #mbox-cells = <1>;
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/Zephyr-latest/drivers/wifi/esp_at/
DKconfig.esp_at2 # SPDX-License-Identifier: Apache-2.0
18 running ESP-AT firmware (https://github.com/espressif/esp-at).
38 int "Stack size for the Espressif esp wifi driver RX thread"
41 This stack is used by the Espressif ESP RX thread.
44 int "Priority of RX thread"
47 Priority of thread used for processing RX data.
54 to the rest of the network stack, letting the rx thread continue
70 int "Modem RX buffer count"
73 Number of preallocated RX buffers used by modem command handler.
76 int "Modem RX buffer size"
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/Zephyr-latest/drivers/gpio/
Dgpio_intel.c2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 ((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
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/Zephyr-latest/drivers/sensor/st/lis2dh/
Dlis2dh_spi.c1 /* ST Microelectronics LIS2DH 3-axis accelerometer driver
5 * SPDX-License-Identifier: Apache-2.0
29 const struct lis2dh_config *cfg = dev->config; in lis2dh_raw_read()
49 const struct spi_buf_set rx = { in lis2dh_raw_read() local
56 return -EIO; in lis2dh_raw_read()
63 if (spi_transceive_dt(&cfg->bus_cfg.spi, &tx, &rx)) { in lis2dh_raw_read()
64 return -EIO; in lis2dh_raw_read()
73 const struct lis2dh_config *cfg = dev->config; in lis2dh_raw_write()
92 return -EIO; in lis2dh_raw_write()
99 if (spi_write_dt(&cfg->bus_cfg.spi, &tx)) { in lis2dh_raw_write()
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/Zephyr-latest/drivers/sensor/adi/adxl367/
Dadxl367_spi.c1 /* adxl367_spi.c - SPI routines for ADXL367 driver
7 * SPDX-License-Identifier: Apache-2.0
22 const struct adxl367_dev_config *config = dev->config; in adxl367_bus_access()
50 const struct spi_buf_set rx = { in adxl367_bus_access() local
57 return spi_transceive_dt(&config->spi, &tx, &rx); in adxl367_bus_access()
62 return spi_write_dt(&config->spi, &tx); in adxl367_bus_access()
90 uint32_t mask, in adxl367_spi_reg_write_mask() argument
101 tmp &= ~mask; in adxl367_spi_reg_write_mask()
116 struct adxl367_data *data = dev->data; in adxl367_spi_init()
117 const struct adxl367_dev_config *config = dev->config; in adxl367_spi_init()
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/Zephyr-latest/boards/m5stack/m5stack_core2/
Dgrove_connectors.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "grove-header";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio1 1 0>, /* D0/SCL/RX */
/Zephyr-latest/modules/canopennode/
DCO_driver.c4 * SPDX-License-Identifier: Apache-2.0
75 if (!CANmodule || !CANmodule->rx_array || !CANmodule->configured) { in canopen_detach_all_rx_filters()
79 for (i = 0U; i < CANmodule->rx_size; i++) { in canopen_detach_all_rx_filters()
80 if (CANmodule->rx_array[i].filter_id != -ENOSPC) { in canopen_detach_all_rx_filters()
81 can_remove_rx_filter(CANmodule->dev, in canopen_detach_all_rx_filters()
82 CANmodule->rx_array[i].filter_id); in canopen_detach_all_rx_filters()
83 CANmodule->rx_array[i].filter_id = -ENOSPC; in canopen_detach_all_rx_filters()
98 /* Loop through registered rx buffers in priority order */ in canopen_rx_callback()
99 for (i = 0; i < CANmodule->rx_size; i++) { in canopen_rx_callback()
100 buffer = &CANmodule->rx_array[i]; in canopen_rx_callback()
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