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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay4 * SPDX-License-Identifier: Apache-2.0
9 sram-ext = &memc;
17 /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
20 is-ram;
21 dev-size = <DT_SIZE_M(64)>;
22 dev-type = <0x5D>;
23 dev-id = <0x0D>;
24 dev-density = <0xE040>;
25 reset-delay-us = <50>;
26 read-cs-idle-min-ns = <18>;
[all …]
/Zephyr-latest/drivers/spi/
Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
57 int mode; in spi_numaker_configure() local
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
62 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
66 if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) { in spi_numaker_configure()
[all …]
Dspi_b91.c4 * SPDX-License-Identifier: Apache-2.0
38 #define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
44 #define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
55 pin = config->cs_pin[i]; in spi_b91_hw_cs_disable()
59 if (config->peripheral_id == PSPI_MODULE) { in spi_b91_hw_cs_disable()
87 if (config->slave >= CHIP_SELECT_COUNT) { in spi_b91_config_cs()
88 LOG_ERR("Slave %d not supported (max. %d)", config->slave, CHIP_SELECT_COUNT - 1); in spi_b91_config_cs()
95 cs_pin = b91_config->cs_pin[cs_id]; in spi_b91_config_cs()
98 if ((cs_pin == 0) && (cs_id == config->slave)) { in spi_b91_config_cs()
99 LOG_ERR("cs%d-pin is not defined in device tree", config->slave); in spi_b91_config_cs()
[all …]
Dspi_dw.c6 * SPDX-License-Identifier: Apache-2.0
11 /* spi_dw.c - Designware SPI driver implementation */
47 spi_context_is_slave(&spi->ctx)); in spi_dw_is_slave()
52 struct spi_dw_data *spi = dev->data; in completed()
53 struct spi_context *ctx = &spi->ctx; in completed()
59 if (spi_context_tx_on(&spi->ctx) || in completed()
60 spi_context_rx_on(&spi->ctx)) { in completed()
75 if (spi_cs_is_gpio(ctx->config)) { in completed()
85 spi_context_complete(&spi->ctx, dev, error); in completed()
90 const struct spi_dw_config *info = dev->config; in push_data()
[all …]
Dspi_oc_simple.c4 * SPDX-License-Identifier: Apache-2.0
41 if (spi_context_configured(&spi->ctx, config)) { in spi_oc_simple_configure()
46 if (config->operation & SPI_HALF_DUPLEX) { in spi_oc_simple_configure()
47 LOG_ERR("Half-duplex not supported"); in spi_oc_simple_configure()
48 return -ENOTSUP; in spi_oc_simple_configure()
51 /* Simple SPI only supports master mode */ in spi_oc_simple_configure()
52 if (spi_context_is_slave(&spi->ctx)) { in spi_oc_simple_configure()
53 LOG_ERR("Slave mode not supported"); in spi_oc_simple_configure()
54 return -ENOTSUP; in spi_oc_simple_configure()
57 if ((config->operation & (SPI_MODE_LOOP | SPI_TRANSFER_LSB)) || in spi_oc_simple_configure()
[all …]
Dspi_bitbang.c2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
35 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
36 LOG_ERR("Slave mode not supported"); in spi_bitbang_configure()
37 return -ENOTSUP; in spi_bitbang_configure()
40 if (config->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure()
49 return -ENOTSUP; in spi_bitbang_configure()
52 data->bits = bits; in spi_bitbang_configure()
[all …]
/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.c4 * SPDX-License-Identifier: Apache-2.0
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
73 LOG_DBG("target MCLK is %u", bespoke->mclk_rate); in sai_mclk_config()
79 mclk_config.mclkHz = bespoke->mclk_rate; in sai_mclk_config()
82 SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config); in sai_mclk_config()
84 set_msel(data->regmap, msel); in sai_mclk_config()
96 data = dev->data; in sai_isr()
[all …]
Dsai.h3 * SPDX-License-Identifier: Apache-2.0
36 #define _SAI_CLOCK_INDEX_ARRAY(inst)\ argument
37 LISTIFY(DT_INST_PROP_LEN_OR(inst, clocks, 0), IDENTITY_VARGS, (,))
40 #define _SAI_GET_CLOCK_ID(clock_idx, inst)\ argument
41 DT_INST_PHA_BY_IDX_OR(inst, clocks, clock_idx, name, 0x0)
44 #define _SAI_GET_CLOCK_NAME(clock_idx, inst)\ argument
45 DT_INST_PROP_BY_IDX(inst, clock_names, clock_idx)
48 #define _SAI_CLOCK_ID_ARRAY(inst)\ argument
49 FOR_EACH_FIXED_ARG(_SAI_GET_CLOCK_ID, (,), inst, _SAI_CLOCK_INDEX_ARRAY(inst))
51 /* used to convert the clock-names property into an array of clock names */
[all …]
/Zephyr-latest/drivers/serial/
Duart_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
50 /* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */ in uart1_wui_isr()
51 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart1_wui_isr()
54 /* Refresh console expired time if got UART Rx wake-up event */ in uart1_wui_isr()
63 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart1_wui_isr()
70 /* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */ in uart2_wui_isr()
71 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart2_wui_isr()
74 /* Refresh console expired time if got UART Rx wake-up event */ in uart2_wui_isr()
83 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart2_wui_isr()
90 const struct uart_it8xxx2_config *const config = dev->config; in uart_it8xxx2_pm_action()
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Duart_npcx.c4 * SPDX-License-Identifier: Apache-2.0
27 struct uart_reg *inst; member
33 /* int-mux configuration */
105 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) { in uart_npcx_pm_policy_state_lock_get()
113 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) { in uart_npcx_pm_policy_state_lock_put()
120 static int uart_set_npcx_baud_rate(struct uart_reg *const inst, int baud_rate, int src_clk) in uart_set_npcx_baud_rate() argument
124 * - 115200 in uart_set_npcx_baud_rate()
125 * - 3000000 in uart_set_npcx_baud_rate()
129 inst->UPSR = 0x38; in uart_set_npcx_baud_rate()
130 inst->UBAUD = 0x01; in uart_set_npcx_baud_rate()
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_npcx_controller.c4 * SPDX-License-Identifier: Apache-2.0
15 * support for a two-wire SMBus/I2C synchronous serial interface. The following
21 * +<----------------+<----------------------+
23 * +------+ +------------+ | +------- ----+ | +------- -------+ |
24 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
25 * | +------+ +------------+ +------------+ Yes +---------------+ |
27 * | +-----------+ |
28 * +--------------------------------------------| WAIT_STOP |<------------+
29 * STOP is completed +-----------+ Issue STOP
35 * +<-----------------+<---------------------+
[all …]
/Zephyr-latest/drivers/ps2/
Dps2_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
60 const struct ps2_xec_config * const cfg = dev->config; in ps2_xec_slp_en_clr()
62 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); in ps2_xec_slp_en_clr()
82 const struct ps2_xec_config * const cfg = dev->config; in ps2_xec_slp_en_clr()
84 if (cfg->pcr_pos == MCHP_PCR3_PS2_0_POS) { in ps2_xec_slp_en_clr()
110 const struct ps2_xec_config * const config = dev->config; in ps2_xec_configure()
111 struct ps2_xec_data * const data = dev->data; in ps2_xec_configure()
112 struct ps2_regs * const regs = config->regs; in ps2_xec_configure()
117 return -EINVAL; in ps2_xec_configure()
120 data->callback_isr = callback_isr; in ps2_xec_configure()
[all …]
Dps2_npcx_controller.c4 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/dt-bindings/clock/npcx_clock.h>
30 * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
39 * The max duration of a PS/2 clock is about 100 micro-seconds.
56 * (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
71 ((struct ps2_reg *)((const struct ps2_npcx_ctrl_config *)(dev)->config)->base)
81 struct ps2_npcx_ctrl_data *const data = dev->data; in ps2_npcx_ctrl_configure()
85 return -EINVAL; in ps2_npcx_ctrl_configure()
89 return -EINVAL; in ps2_npcx_ctrl_configure()
92 k_sem_take(&data->lock, K_FOREVER); in ps2_npcx_ctrl_configure()
[all …]
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
29 #define _ESAI_FIFO_DEPTH(inst)\ argument
30 FSL_FEATURE_ESAI_FIFO_SIZEn(UINT_TO_ESAI(DT_INST_REG_ADDR(inst)))
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
37 #define ESAI_FIFO_DEPTH(inst)\ argument
38 DT_INST_PROP_OR(inst, fifo_depth, _ESAI_FIFO_DEPTH(inst))
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
43 #define ESAI_TX_FIFO_WATERMARK(inst)\ argument
44 DT_INST_PROP_OR(inst, tx_fifo_watermark, (_ESAI_FIFO_DEPTH(inst) / 2))
[all …]
Desai.c4 * SPDX-License-Identifier: Apache-2.0
12 * to want to keep the pins of the data lines in ESAI mode.
25 * by 1 up to 256 (configured via xPM0-xPM7). The resulting
28 * up to 16 (configured via xFP0-xFP3). The resulting signal is
42 return -EINVAL; in esai_get_clock_rate_config()
47 return -EINVAL; in esai_get_clock_rate_config()
52 return -EINVAL; in esai_get_clock_rate_config()
57 return -EINVAL; in esai_get_clock_rate_config()
63 return -EINVAL; in esai_get_clock_rate_config()
69 return -EINVAL; in esai_get_clock_rate_config()
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
59 erase-cs-idle-min-ns:
[all …]
/Zephyr-latest/subsys/modbus/
Dmodbus_core.c5 * SPDX-License-Identifier: Apache-2.0
18 #define MB_RTU_DEFINE_GPIO_CFG(inst, prop) \ argument
19 static struct gpio_dt_spec prop##_cfg_##inst = { \
20 .port = DEVICE_DT_GET(DT_INST_PHANDLE(inst, prop)), \
21 .pin = DT_INST_GPIO_PIN(inst, prop), \
22 .dt_flags = DT_INST_GPIO_FLAGS(inst, prop), \
25 #define MB_RTU_DEFINE_GPIO_CFGS(inst) \ argument
26 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, de_gpios), \
27 (MB_RTU_DEFINE_GPIO_CFG(inst, de_gpios)), ()) \
28 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, re_gpios), \
[all …]
/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_numaker.c4 * SPDX-License-Identifier: Apache-2.0
36 * by Timer-trigger EADC. To implement this interconnection, TCPC node_id
39 * NOTE: EADC and Timer interrupts needn't enable for Timer-triggered EADC.
49 * (1) DPM-supplied callback
76 #define NUMAKER_SYS_REG_DUMP(dev, reg_name) LOG_INF("SYS: %8s: 0x%08x", #reg_name, SYS->reg_name);
82 LOG_INF("%s: %8s: 0x%08x", #port, #reg_name, port->reg_name);
98 utcpd_base->reg_name = (val); \
110 LOG_ERR("UTCPD register (%s) write timeout, force-write", #reg_name); \
112 utcpd_base->reg_name = (val); \
137 LOG_ERR("UTCPD register (0x%04x) write timeout, force-write", reg_offset); \
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl345/
Dadxl345.c4 * SPDX-License-Identifier: Apache-2.0
23 return device_is_ready(bus->i2c.bus); in adxl345_bus_is_ready_i2c()
29 const struct adxl345_dev_config *cfg = dev->config; in adxl345_reg_access_i2c()
32 return i2c_burst_read_dt(&cfg->bus.i2c, reg_addr, data, length); in adxl345_reg_access_i2c()
34 return i2c_burst_write_dt(&cfg->bus.i2c, reg_addr, data, length); in adxl345_reg_access_i2c()
42 return spi_is_ready_dt(&bus->spi); in adxl345_bus_is_ready_spi()
48 const struct adxl345_dev_config *cfg = dev->config; in adxl345_reg_access_spi()
51 const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)}; in adxl345_reg_access_spi() local
60 ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx); in adxl345_reg_access_spi()
63 ret = spi_write_dt(&cfg->bus.spi, &tx); in adxl345_reg_access_spi()
[all …]
/Zephyr-latest/include/zephyr/drivers/can/
Dcan_mcan.h5 * SPDX-License-Identifier: Apache-2.0
286 /* Rx FIFO 0 Configuration register */
293 /* Rx FIFO 0 Status register */
301 /* Rx FIFO 0 Acknowledge register */
305 /* Rx Buffer Configuration register */
309 /* Rx FIFO 1 Configuration register */
316 /* Rx FIFO 1 Status register */
324 /* Rx FIFO 1 Acknowledge register */
328 /* Rx Buffer/FIFO Element Size Configuration register */
399 * @name Indexes for the cells in the devicetree bosch,mram-cfg property
[all …]
/Zephyr-latest/drivers/bluetooth/hci/
Dhci_ifx_psoc6_bless.c5 * SPDX-License-Identifier: Apache-2.0
102 struct psoc6_bless_data *hci = dev->data; in psoc6_bless_events_handler()
114 switch (hci_rx->packetType) { in psoc6_bless_events_handler()
116 buf = bt_buf_get_evt(hci_rx->data[0], 0, K_NO_WAIT); in psoc6_bless_events_handler()
118 LOG_ERR("Failed to allocate the buffer for RX: EVENT "); in psoc6_bless_events_handler()
126 LOG_ERR("Failed to allocate the buffer for RX: ACL "); in psoc6_bless_events_handler()
139 if (buf_tailroom < hci_rx->dataLength) { in psoc6_bless_events_handler()
140 LOG_WRN("Not enough space for rx data"); in psoc6_bless_events_handler()
143 net_buf_add_mem(buf, hci_rx->data, hci_rx->dataLength); in psoc6_bless_events_handler()
144 hci->recv(dev, buf); in psoc6_bless_events_handler()
[all …]
/Zephyr-latest/drivers/mipi_dsi/
Ddsi_stm32.c7 * SPDX-License-Identifier: Apache-2.0
61 const struct mipi_dsi_stm32_config *config = dev->config; in mipi_dsi_stm32_log_config()
62 struct mipi_dsi_stm32_data *data = dev->data; in mipi_dsi_stm32_log_config()
64 LOG_DBG("DISPLAY: pix %d kHz, lane %d kHz", data->pixel_clk_khz, data->lane_clk_khz); in mipi_dsi_stm32_log_config()
66 LOG_DBG(" AutomaticClockLaneControl 0x%x", data->hdsi.Init.AutomaticClockLaneControl); in mipi_dsi_stm32_log_config()
67 LOG_DBG(" TXEscapeCkdiv %u", data->hdsi.Init.TXEscapeCkdiv); in mipi_dsi_stm32_log_config()
68 LOG_DBG(" NumberOfLanes %u", data->hdsi.Init.NumberOfLanes); in mipi_dsi_stm32_log_config()
69 LOG_DBG(" PLLNDIV %u", data->pll_init.PLLNDIV); in mipi_dsi_stm32_log_config()
70 LOG_DBG(" PLLIDF %u", data->pll_init.PLLIDF); in mipi_dsi_stm32_log_config()
71 LOG_DBG(" PLLODF %u", data->pll_init.PLLODF); in mipi_dsi_stm32_log_config()
[all …]
/Zephyr-latest/drivers/i3c/
Di3c_npcx.c4 * SPDX-License-Identifier: Apache-2.0
61 #define MSTATUS_STATE_NORMACT 0x3 /* SDR message mode */
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
163 uint8_t ppbaud; /* Push-Pull high period */
164 uint8_t pplow; /* Push-Pull low period */
165 uint8_t odhpp; /* Open-Drain high period */
166 uint8_t odbaud; /* Open-Drain low period */
[all …]
/Zephyr-latest/drivers/dma/
Ddma_xilinx_axi_dma.c7 * SPDX-License-Identifier: Apache-2.0
40 /* internal DMA error, e.g., 0-length transfer */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
84 /* run-stop */
118 /* RS (run-stop) in DMACR is 0 and operations completed; writing tail does nothing */
147 /* in-memory descriptor, read by the DMA, that instructs it how many bits to transfer from which */
150 /* next descriptor[31:6], bits 5-0 reserved */
166 /* application-specific fields used, e.g., to enable checksum offloading */
195 /* transfer source address for "direct register mode"[31:0] */
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl362/
Dadxl362.c1 /* adxl362.c - ADXL362 Three-Axis Digital Accelerometers */
6 * SPDX-License-Identifier: Apache-2.0
29 const struct adxl362_config *cfg = dev->config; in adxl362_reg_access()
46 const struct spi_buf_set rx = { in adxl362_reg_access() local
53 return spi_transceive_dt(&cfg->bus, &tx, &rx); in adxl362_reg_access()
58 return spi_write_dt(&cfg->bus, &tx); in adxl362_reg_access()
162 return -EINVAL; in adxl362_freq_to_odr_val()
173 return -EINVAL; in adxl362_freq_to_odr_val()
197 return -EINVAL; in adxl362_range_to_reg_val()
203 struct adxl362_data *adxl362_data = dev->data; in adxl362_set_range()
[all …]

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