Lines Matching +full:rx +full:- +full:inst +full:- +full:mode
5 * SPDX-License-Identifier: Apache-2.0
60 const struct ps2_xec_config * const cfg = dev->config; in ps2_xec_slp_en_clr()
62 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); in ps2_xec_slp_en_clr()
82 const struct ps2_xec_config * const cfg = dev->config; in ps2_xec_slp_en_clr()
84 if (cfg->pcr_pos == MCHP_PCR3_PS2_0_POS) { in ps2_xec_slp_en_clr()
110 const struct ps2_xec_config * const config = dev->config; in ps2_xec_configure()
111 struct ps2_xec_data * const data = dev->data; in ps2_xec_configure()
112 struct ps2_regs * const regs = config->regs; in ps2_xec_configure()
117 return -EINVAL; in ps2_xec_configure()
120 data->callback_isr = callback_isr; in ps2_xec_configure()
127 temp = regs->TRX_BUFF; in ps2_xec_configure()
128 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_configure()
130 ps2_xec_girq_clr(config->girq_id, config->girq_bit); in ps2_xec_configure()
132 /* Enable FSM and init instance in rx mode*/ in ps2_xec_configure()
133 regs->CTRL = MCHP_PS2_CTRL_EN_POS; in ps2_xec_configure()
138 ps2_xec_girq_en(config->girq_id, config->girq_bit); in ps2_xec_configure()
140 k_sem_give(&data->tx_lock); in ps2_xec_configure()
148 const struct ps2_xec_config * const config = dev->config; in ps2_xec_write()
149 struct ps2_xec_data * const data = dev->data; in ps2_xec_write()
150 struct ps2_regs * const regs = config->regs; in ps2_xec_write()
155 if (k_sem_take(&data->tx_lock, K_NO_WAIT)) { in ps2_xec_write()
156 return -EACCES; in ps2_xec_write()
158 /* Allow the PS2 controller to complete a RX transaction. This in ps2_xec_write()
164 while (((regs->STATUS & in ps2_xec_write()
173 return -ETIMEDOUT; in ps2_xec_write()
179 regs->CTRL = 0x00; in ps2_xec_write()
182 temp = regs->TRX_BUFF; in ps2_xec_write()
184 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_write()
186 /* Switch the interface to TX mode and enable state machine */ in ps2_xec_write()
187 regs->CTRL = MCHP_PS2_CTRL_TR_TX | MCHP_PS2_CTRL_EN; in ps2_xec_write()
189 /* Write value to TX/RX register */ in ps2_xec_write()
190 regs->TRX_BUFF = value; in ps2_xec_write()
192 k_sem_give(&data->tx_lock); in ps2_xec_write()
199 const struct ps2_xec_config * const config = dev->config; in ps2_xec_inhibit_interface()
200 struct ps2_xec_data * const data = dev->data; in ps2_xec_inhibit_interface()
201 struct ps2_regs * const regs = config->regs; in ps2_xec_inhibit_interface()
203 if (k_sem_take(&data->tx_lock, K_MSEC(10)) != 0) { in ps2_xec_inhibit_interface()
204 return -EACCES; in ps2_xec_inhibit_interface()
207 regs->CTRL = 0x00; in ps2_xec_inhibit_interface()
208 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_inhibit_interface()
209 ps2_xec_girq_clr(config->girq_id, config->girq_bit); in ps2_xec_inhibit_interface()
210 NVIC_ClearPendingIRQ(config->isr_nvic); in ps2_xec_inhibit_interface()
212 k_sem_give(&data->tx_lock); in ps2_xec_inhibit_interface()
219 const struct ps2_xec_config * const config = dev->config; in ps2_xec_enable_interface()
220 struct ps2_xec_data * const data = dev->data; in ps2_xec_enable_interface()
221 struct ps2_regs * const regs = config->regs; in ps2_xec_enable_interface()
223 ps2_xec_girq_clr(config->girq_id, config->girq_bit); in ps2_xec_enable_interface()
224 regs->CTRL = MCHP_PS2_CTRL_EN; in ps2_xec_enable_interface()
226 k_sem_give(&data->tx_lock); in ps2_xec_enable_interface()
234 const struct ps2_xec_config *const devcfg = dev->config; in ps2_xec_pm_action()
235 struct ps2_regs * const regs = devcfg->regs; in ps2_xec_pm_action()
240 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
244 if (devcfg->wakerx_gpio.port != NULL) { in ps2_xec_pm_action()
246 &devcfg->wakerx_gpio, in ps2_xec_pm_action()
253 ps2_xec_girq_dis(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
254 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
256 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in ps2_xec_pm_action()
257 regs->CTRL |= MCHP_PS2_CTRL_EN; in ps2_xec_pm_action()
261 if (devcfg->wakeup_source) { in ps2_xec_pm_action()
265 ps2_xec_girq_clr(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
266 ps2_xec_girq_en(devcfg->girq_id_wk, devcfg->girq_bit_wk); in ps2_xec_pm_action()
267 if (devcfg->wakerx_gpio.port != NULL) { in ps2_xec_pm_action()
269 &devcfg->wakerx_gpio, in ps2_xec_pm_action()
277 regs->CTRL &= ~MCHP_PS2_CTRL_EN; in ps2_xec_pm_action()
279 * not define pinctrl-1 for this node. in ps2_xec_pm_action()
281 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in ps2_xec_pm_action()
282 if (ret == -ENOENT) { /* pinctrl-1 does not exist. */ in ps2_xec_pm_action()
288 ret = -ENOTSUP; in ps2_xec_pm_action()
297 const struct ps2_xec_config * const config = dev->config; in ps2_xec_isr()
298 struct ps2_xec_data * const data = dev->data; in ps2_xec_isr()
299 struct ps2_regs * const regs = config->regs; in ps2_xec_isr()
303 status = regs->STATUS; in ps2_xec_isr()
306 ps2_xec_girq_clr(config->girq_id, config->girq_bit); in ps2_xec_isr()
311 regs->CTRL = 0x00; in ps2_xec_isr()
312 if (data->callback_isr) { in ps2_xec_isr()
313 data->callback_isr(dev, regs->TRX_BUFF); in ps2_xec_isr()
319 /* Clear sticky bits and go to read mode */ in ps2_xec_isr()
320 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_isr()
326 /* catch and clear rx error if any */ in ps2_xec_isr()
327 regs->STATUS = MCHP_PS2_STATUS_RW1C_MASK; in ps2_xec_isr()
329 /* Transfer completed, release the lock to enter low per mode */ in ps2_xec_isr()
334 /* The control register reverts to RX automatically after in ps2_xec_isr()
337 regs->CTRL = MCHP_PS2_CTRL_EN; in ps2_xec_isr()
350 const struct ps2_xec_config * const cfg = dev->config; in ps2_xec_init()
351 struct ps2_xec_data * const data = dev->data; in ps2_xec_init()
352 int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in ps2_xec_init()
360 k_sem_init(&data->tx_lock, 0, 1); in ps2_xec_init()
362 cfg->irq_config_func(); in ps2_xec_init()
371 * wakerx-gpios = <MCHP_GPIO_DECODE_115 GPIO_ACTIVE_HIGH>
372 * wakeup-source;
382 #define XEC_PS2_PINCTRL_CFG(inst) PINCTRL_DT_INST_DEFINE(inst) argument
383 #define XEC_PS2_CONFIG(inst) \ argument
384 static const struct ps2_xec_config ps2_xec_config_##inst = { \
385 .regs = (struct ps2_regs * const)(DT_INST_REG_ADDR(inst)), \
386 .isr_nvic = DT_INST_IRQN(inst), \
387 .girq_id = (uint8_t)(DT_INST_PROP_BY_IDX(inst, girqs, 0)), \
388 .girq_bit = (uint8_t)(DT_INST_PROP_BY_IDX(inst, girqs, 1)), \
389 .girq_id_wk = (uint8_t)(DT_INST_PROP_BY_IDX(inst, girqs, 2)), \
390 .girq_bit_wk = (uint8_t)(DT_INST_PROP_BY_IDX(inst, girqs, 3)), \
391 .pcr_idx = (uint8_t)(DT_INST_PROP_BY_IDX(inst, pcrs, 0)), \
392 .pcr_pos = (uint8_t)(DT_INST_PROP_BY_IDX(inst, pcrs, 1)), \
393 .irq_config_func = ps2_xec_irq_config_func_##inst, \
394 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
395 XEC_PS2_PM_WAKEUP(inst) \