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/Zephyr-latest/boards/qemu/riscv64/doc/
Dindex.rst6 The RISCV64 QEMU board configuration is used to emulate the RISCV64 architecture.
13 with toolchain and QEMU support for the RISCV64 architecture is v0.10.2.
43 threadA: Hello World from riscv64!
44 threadB: Hello World from riscv64!
45 threadA: Hello World from riscv64!
46 threadB: Hello World from riscv64!
47 threadA: Hello World from riscv64!
48 threadB: Hello World from riscv64!
49 threadA: Hello World from riscv64!
50 threadB: Hello World from riscv64!
[all …]
/Zephyr-latest/boards/qemu/riscv64/
Dboard.cmake5 set(QEMU_binary_suffix riscv64)
6 set(QEMU_CPU_TYPE_${ARCH} riscv64)
Dboard.yml3 full_name: QEMU Emulation for RISCV64
Dqemu_riscv64.dts6 #include <qemu/virt-riscv64.dtsi>
Dqemu_riscv64_qemu_virt_riscv64_smp.dts6 #include <qemu/virt-riscv64.dtsi>
/Zephyr-latest/tests/arch/riscv/userspace/riscv_gp/
Dtestcase.yaml10 arch.riscv64.riscv_gp.relative_addressing:
13 arch.riscv64.riscv_gp.thread_pointer:
/Zephyr-latest/tests/crypto/mbedtls/
Dtestcase.yaml14 - arch:riscv64:CONFIG_ZTEST_STACK_SIZE=8192
/Zephyr-latest/tests/arch/riscv/fatal/
Dtestcase.yaml11 arch.riscv64.fatal:
/Zephyr-latest/boards/sifive/hifive_unmatched/
Dhifive_unmatched.dtsi9 #include <sifive/riscv64-fu740.dtsi>
/Zephyr-latest/cmake/toolchain/xtools/
Dtarget.cmake6 set(CROSS_COMPILE_TARGET_riscv riscv64-zephyr-elf)
/Zephyr-latest/boards/sifive/hifive_unleashed/doc/
Dindex.rst46 riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
/Zephyr-latest/boards/sifive/hifive_unmatched/doc/
Dindex.rst46 riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
/Zephyr-latest/tests/kernel/fpu_sharing/generic/
Dtestcase.yaml40 kernel.fpu_sharing.generic.riscv64:
/Zephyr-latest/soc/andestech/ae350/
DKconfig41 bool "RISCV64 CPU ISA"
Dpma.c55 /* In riscv64, CSR pmacfg number are even number (0, 2, ...) */
/Zephyr-latest/cmake/toolchain/llvm/
Dtarget.cmake38 set(triple riscv64-unknown-elf)
/Zephyr-latest/boards/beagle/beaglev_fire/doc/
Dindex.rst69 <path_to_zephyr_sdk>/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gdb
/Zephyr-latest/boards/sifive/hifive_unleashed/
Dhifive_unleashed.dtsi9 #include <sifive/riscv64-fu540.dtsi>
/Zephyr-latest/boards/microchip/m2gl025_miv/doc/
Dindex.rst53 <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
/Zephyr-latest/boards/microchip/mpfs_icicle/doc/
Dindex.rst58 <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
/Zephyr-latest/doc/services/dsp/
Dindex.rst24 RISCV64 Unoptimized
/Zephyr-latest/boards/snps/nsim/arc_v/doc/
Dindex.rst119 * you should use :file:`riscv64-zephyr-elf-gdb`
126 riscv64-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf
/Zephyr-latest/doc/develop/tools/
Dclion.rst163 (for example, **riscv64-zephyr-elf-gdb-py**) and check that Python
/Zephyr-latest/boards/andestech/adp_xc7k_ae350/doc/
Dindex.rst268 riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
311 ./riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
/Zephyr-latest/lib/utils/
Dbitarray.c522 * So don't use this on RISCV64. in sys_bitarray_alloc()