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/Zephyr-latest/dts/bindings/pwm/
Dtelink,b91-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: Telink B91 PWM
7 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
9 compatible: "telink,b91-pwm"
13 pinctrl-0:
16 clock-frequency:
19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
21 clk32k-ch0-enable:
23 description: Enable 32K Source Clock for PWM Channel 0
25 clk32k-ch1-enable:
[all …]
Dnxp,ftm-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP FlexTimer Module (FTM) PWM controller
6 compatible: "nxp,ftm-pwm"
8 include: [pwm-controller.yaml, "nxp,ftm.yaml", "pinctrl-device.yaml"]
11 "#pwm-cells":
14 pinctrl-0:
17 clock-source:
21 - "system"
22 - "fixed"
23 - "external"
[all …]
Dnxp,s32-emios-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
5 NXP S32 eMIOS PWM node for S32 SoCs. Each channel in eMIOS can be configured
6 to use for PWM operation. There are several PWM modes supported by this module,
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
16 emios0_pwm: pwm {
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
[all …]
Dnordic,nrf-sw-pwm.yaml1 description: nRFx S/W PWM
3 compatible: "nordic,nrf-sw-pwm"
5 include: [pwm-controller.yaml, base.yaml]
12 Reference to TIMER or RTC instance for generating PWM output signals
14 clock-prescaler:
18 Clock prescaler for RTC or TIMER used for generating PWM output signals.
20 RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM
23 TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation.
25 channel-gpios:
26 type: phandle-array
[all …]
Dmicrochip,xec-pwmbbled.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC PWM using BBLED hardware
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
27 clock-select:
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
36 - "PWM_BBLED_CLK_48M"
[all …]
Dinfineon,xmc4xxx-ccu8-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Infineon XMC4XXX PWM Capture Compare Unit 8 (CCU8) module
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
14 The dead time ensures that there is a delay before the PWM state
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
[all …]
Dintel,blinky-pwm.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: Intel blinky PWM
7 compatible: "intel,blinky-pwm"
9 include: [pwm-controller.yaml, base.yaml]
15 reg-offset:
18 description: PWM control register offset from base
20 clock-frequency:
23 description: PWM Peripheral Clock frequency in Hz
25 max-pins:
30 "#pwm-cells":
[all …]
Datmel,sam-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Atmel SAM PWM
6 compatible: "atmel,sam-pwm"
9 - name: base.yaml
10 - name: pwm-controller.yaml
11 - name: pinctrl-device.yaml
26 description: Clock prescaler at the input of the PWM (0 to 10)
31 description: Clock divider at the input of the PWM (1 to 255)
33 "#pwm-cells":
36 pwm-cells:
[all …]
Dnuvoton,npcx-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, NPCX Pulse Width Modulator (PWM) node
6 compatible: "nuvoton,npcx-pwm"
8 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
15 pinctrl-0:
17 pinctrl-names:
19 pwm-channel:
22 A index to indicate PWM module that generates a single PWM signal.
23 Please don't overwrite it in the board-level DT driver.
24 clock-bus:
[all …]
Dinfineon,xmc4xxx-ccu4-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Infineon XMC4XXX PWM Capture Compare Unit 4 (CCU4) module
12 dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
14 The CCU4 modules uses the CCU clock source. Each slice applies a separate
15 prescalar which divides the clock.
18 A node can define a 'pwm' field, usually referenced in a 'pwms'
19 property, where the entries include the PWM module phandle,
24 The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
26 slice-prescaler = <15 15 15 15>;
27 pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dpwm-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 An external clock signal driven by a PWM pin.
7 The devicetree must define a clock node:
11 compatible = "pwm-clock";
12 #clock-cells = <1>;
16 This will create a device node with a clock-controller
17 API. Internally the device node will use PWM API to start the
18 clock signals at 1MHz. Note that the PWM_HZ() macro converts the
20 errors if the clock frequency is not an integer number of nanoseconds.
21 The clock frequency can be explicitly set using the clock-frequency
[all …]
/Zephyr-latest/drivers/clock_control/
DKconfig.pwm2 # SPDX-License-Identifier: Apache-2.0
5 bool "Generic PWM clock"
8 select PWM
10 Enable generic PWM clock.
13 int "Initialization priority of the pwm clock device"
17 Initialization priority of the PWM clock device. Must be
18 lower priority than PWM.
/Zephyr-latest/tests/drivers/clock_control/pwm_clock/
Dtestcase.yaml2 drivers.clock.pwm_clock:
3 filter: dt_compat_enabled("pwm-clock") and dt_compat_enabled("test-clock-control-pwm-clock")
5 - drivers
6 - clock
7 - pwm
/Zephyr-latest/drivers/pwm/
Dpwm_npcx.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/pwm.h>
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
20 /* 16-bit period cycles/prescaler in NPCX PWM modules */
24 /* PWM clock sources */
30 /* PWM heart-beat mode selection */
38 /* pwm controller base address */
40 /* clock configuration */
48 /* PWM cycles per second */
52 /* PWM local functions */
[all …]
Dpwm_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/pwm.h>
12 #include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
28 /* PWM channel duty cycle register */
30 /* PWM channel clock source selection register */
32 /* PWM channel clock source gating register */
34 /* PWM channel output polarity register */
36 /* PWM channel */
38 /* PWM prescaler control register base */
40 /* Select PWM prescaler that output to PWM channel */
[all …]
Dpwm_sam.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/pwm.h>
26 Pwm *regs;
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec()
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec()
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles()
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles() local
56 return -EINVAL; in sam_pwm_set_cycles()
60 return -ENOTSUP; in sam_pwm_set_cycles()
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &sci2;
12 /delete-node/ &sci3;
13 /delete-node/ &ioport6;
14 /delete-node/ &ioport7;
15 /delete-node/ &ioport8;
20 compatible = "mmio-sram";
25 compatible = "renesas,ra-spi";
[all …]
/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "twr_ke18f-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
27 pwm-led0 = &orange_pwm_led;
28 pwm-led1 = &yellow_pwm_led;
29 pwm-led2 = &green_pwm_led;
[all …]
/Zephyr-latest/dts/arm/adi/max32/
Dmax32xxx.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &flc0;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-latest/samples/drivers/led/pwm/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11
11 * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13
12 * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5
13 * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19
16 * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1)
17 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
18 * 255 full on. BBLED PWM is 8-bit.
19 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
[all …]
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13
11 * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15
12 * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17
14 * BBLED hardware divides input clock (32KHz or 48MHz) by (256 * (prescalar+1)
15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
17 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
18 * Due to all the above we use 50 ms for DT PWM period.
[all …]
/Zephyr-latest/tests/drivers/clock_control/pwm_clock/dts/bindings/
Dtest-clock-control-clock-pwm.yaml1 description: Example binding for a node using a PWM clock
3 compatible: "test-clock-control-pwm-clock"
10 description: Clock phandle array
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_pwm.h4 * SPDX-License-Identifier: Apache-2.0
16 /* PWM Count On register */
20 /* PWM Count Off register */
24 /* PWM Configuration Register */
28 * Enable and start PWM. Clearing this bit resets internal counters.
33 /* Clock select */
45 * Clock pre-divider
46 * Clock divider value = pre-divider + 1
57 /* PWM input frequencies selected in configuration register. */
62 * PWM Frequency =
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f0.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
[all …]
/Zephyr-latest/soc/nxp/imx/imx7d/
Dsoc_clk_freq.h4 * SPDX-License-Identifier: Apache-2.0
19 * @brief Get clock frequency applies to the PWM module
21 * @param base PWM base pointer.
22 * @return clock frequency (in HZ) applies to the PWM module
31 /*! @brief Root control names for root clock setting. */
39 /*! @brief Clock source enumeration for PWM peripheral. */

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