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/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core/src/
Dcore_std_files.md16 The CMSIS-Core Standard file implement all attributes specific to Arm processor cores and generally…
24 ### CMSIS-Core Processor Files {#cmsis_processor_files}
26 The CMSIS-Core processor files define the core peripherals and provide helper functions for their a…
28 …g convention `core_<cpu>.h`, with one file available for each supported processor `<cpu>` as liste…
30 Header File | Target Processor Core
33 ┣ �� core_cm0.h | Cortex-M0 processor
34 ┣ �� core_cm0plus.h | Cortex-M0+ processor
35 ┣ �� core_cm1.h | Cortex-M1 processor
36 ┣ �� core_cm3.h | Cortex-M3 processor
37 ┣ �� core_cm4.h | Cortex-M4 processor
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Dmainpage.md3 …n-time system for Arm Cortex-M devices and gives the user access to the processor core and the dev…
7 …- **Hardware Abstraction Layer (HAL)** for Cortex-M processor registers with standardized definit…
41 ## Processor Support {#ref_v6-v8M}
61 CMSIS-Core also supports the following Cortex-M processor variants:
63 …- [Cortex-M1](https://developer.arm.com/Processors/Cortex-M1) is a processor designed specifically…
66 …eveloper.arm.com/Processors/Cortex-M35P) is a tamper resistant Cortex-M processor with optional so…
72 … **mainline** (full-featured with optional SIMD, floating-point, and co-processor extensions). Bot…
Dref_device_caps.txt48 <td>Processor has no FPU. The value set for \ref __FPU_DP.</td>
53 <td>Processor with FPU with single precision.</td>
58 <td>Processor with FPU with double precision.</td>
79 <td>Processor has no FPU. The value set for \ref __FPU_DP. </td>
84 <td>Processor with FPU with single precision.</td>
89 <td>Processor with FPU with double precision.</td>
Dusing.md9 - \ref device_h_pg gives access to processor core and all peripherals.
15 The \ref system_c_pg performs the setup for the processor clock. The variable \ref SystemCoreClock …
109 // The processor clock is initialized by CMSIS startup + system file
187 …used as a target for embedded programs, with execution, for example, on processor simulation model…
193 The CMSIS Processor and Core Peripheral files allow also to create generic libraries.
196 …RIC` and include the relevant `core_<cpu>.h` CMSIS CPU & Core Access header file for the processor.
206 To select the processor, the source code uses the defines `CORTEX_M7`, `CORTEX_M4`, `CORTEX_M3`, `C…
222 #error "Processor not specified or unsupported."
Dref_nvic.txt173 The Vector Table defines the entry addresses of the processor exceptions and the
187 Processor Exceptions
190 exception vectors of the processor are defined. The vector table below
191 shows the exception vectors of a Armv8-M Mainline processor. Other processor
216 Following the processor exception vectors, the vector table contains also the
378 - Negative IRQn values represent processor core exceptions (internal interrupts).
386 /****** Cortex-M3 Processor Exceptions/Interrupt Numbers **************************/
599 - Each external interrupt has an active status bit. When the processor starts the interrupt
601 - When an ISR is preempted and the processor executes another interrupt handler, the
616 device specific interrupt, or processor exception. The \em priority specifies
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Dref_version_ctrl.txt7 … \ref __CORTEX_M , \ref __CORTEX_SC or \ref __STAR_MC that identify the processor core variant des…
9 Additionally each processor header file includes the <b>cmsis_version.h</b> file with \ref __CM_CMS…
11 This allows application code and middleware components to verify the target processor and the CMSIS…
Dref_compiler_ctrl.txt17 …cture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
25 …ode for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
33 … point extension. This architecture is for example implemented by the Cortex-M4 processor with FPU.
46 This architecture is for example implemented by the Cortex-M23 processor.
55 This architecture is for example implemented by the Cortex-M33 processor.
64 This architecture is for example implemented by the Cortex-M55 processor.
299 processor core and compiler settings.
320 processor core and compiler settings.
341 processor core and compiler settings.
362 processor core and compiler settings.
Dref_core_reg.txt17 when the processor is in thread mode and, if implemented, indicates whether the FPU state is
36 - The processor can be in user state or privileged state when running in thread mode.
38 - On reset, the processor is in thread mode with privileged access rights.
53 when the processor is in thread mode and, if implemented, indicates whether the FPU state is
61 - Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
67 - Writeable only when the processor is in privileged state.
68 - Can be used to switch the processor to user state (thread mode).
78 - The processor can be in user state or privileged state when running in thread mode.
80 - On reset, the processor is in thread mode with privileged access rights.
198 - =1 Indicates that that the processor is in Thumb state.
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Dcore_device_h.md14 - Negative IRQn values represent processor core exceptions (internal interrupts).
25 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
43 ## Configuration of the Processor and Core Peripherals {#core_config_sect}
48 The following tables list the <i>\#defines</i> along with the possible values for each processor co…
614 The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.
625 #include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core_A/src/
Dtemplate.md10 ## CMSIS-Core Processor Files {#CMSIS_Processor_files}
12 The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core\\Include. These …
16 Header File | Target Processor Core
63 `Cortex-A#` | The specific Cortex-A processor name, for example `Cortex-A9`
75 - Exception vectors of the Cortex-A Processor with weak functions that implement default routines.
83 An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below.
127 - IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
128 - IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
129 - IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
146 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
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Dref_compiler_ctrl.txt19 …ode for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
209 processor core and compiler settings.
230 processor core and compiler settings.
251 processor core and compiler settings.
272 processor core and compiler settings.
307 \details Wait For Event is a hint instruction that permits the processor to enter
313 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
326 \details Causes the processor to enter Debug state.
Dmainpage.md3 … run-time system for a Cortex-A device and gives the user access to the processor core and the dev…
6 …- **Hardware Abstraction Layer (HAL)** for Cortex-A processor registers with standardized definit…
36 ## Processor Support {#ref_v7A}
Dusing.md6 - \ref device_h_pg gives access to processor core and all peripherals.
23 The \ref system_c_pg performs the setup for the processor clock and the initialization of memory ca…
119 …used as a target for embedded programs, with execution, for example, on processor simulation model…
Dref_core_reg.txt34 | [6] | SMP | Enables coherent requests to the processor. |
51 | [6] | SMP | Enables coherent requests to the processor. |
62 | [6] | SMP | Enables coherent requests to the processor. |
284 \brief The Current Program Status Register (CPSR) holds processor status and control information.
360 \details The M field can contain one of these values which indicates the current processor mode.
757 \brief In a multiprocessor system, the MPIDR provides an additional processor identification
913 \brief The processor uses SP as a pointer to the active stack.
915 The Stack Pointer is banked per processor mode. Accessing the
917 of the current processor execution mode.
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Zone/src/
Dmainpage.md5 - Split of a multi-processor system for single processor views
/cmsis_6-latest/CMSIS/Documentation/Doxygen/General/src/
Dcmsis_sw_pack.md10 ┣ �� Core | Processor files for the [CMSIS-Core (Cortex-M)](../Core/index.html)
11 ┣ �� Core_A | Processor files for the [CMSIS-Core (Cortex-A)](../Core_A/index.html)
Drevision_history.md43 - Added provisional support for processor affinity in SMP systems
391 <td>Introducing processor support for Cortex-M7.
428 <td>Added support for Cortex-M4 processor</td>
436 <td>Added support for Cortex-M0 processor</td>
440 <td>Initial release of CMSIS-Core (Cortex-M) for Cortex-M3 processor</td>
/cmsis_6-latest/CMSIS/Driver/Include/
DDriver_Storage.h51 …INVALID_ADDRESS (0xFFFFFFFFUL) ///< Invalid address within the processor's memory address…
70 …uint32_t executable : 1; ///< This storage block can hold program data; the processor can fe…
120 #define ARM_RETENTION_ACROSS_SLEEP (1U) ///< Data is retained across processor sleep.
121 #define ARM_RETENTION_ACROSS_DEEP_SLEEP (2U) ///< Data is retained across processor deep-sle…
166 … memory_mapped : 1; ///< This storage device has a mapping onto the processor's memory address…
355 …\param[in] addr The address for which we want a resolution to the processor's physical address s…
358 …\return The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRE…
/cmsis_6-latest/CMSIS/Documentation/Doxygen/DAP/src/
Dmainpage.md10 A processor device exposes Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-p…
22 - Access to CoreSight registers of all Cortex processor architectures (Cortex-A/R/M).
/cmsis_6-latest/CMSIS/Documentation/Doxygen/RTOS2/src/
Dref_cmsis_os2_thread.txt42 Processor Mode for Thread Execution
48 …d and unprivileged mode, please refer to the User's Guide of the target processor. But typically f…
50 In **unprivileged processor mode**, the thread :
55 In **privileged processor mode**, the application software can use all the instructions and has acc…
327 In \b unprivileged processor mode, a thread:
334 Refer to the target processor User's Guide for details.
343 In \b privileged processor mode, the application software can use all the instructions and has acce…
367 \param n processor number, starting with n=0 for processor #0. The number of supported processors …
910 The mask indicates on which processor(s) the thread should run (\token{0} indicates on any processo…
931 status = osThreadSetAffinityMask(id, osThreadProcessor(1)); // run thread processor #1
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/cmsis_6-latest/CMSIS/Core/Include/
Dcore_cm0.h187 \brief Type definitions and defines for Cortex-M processor based devices.
494 …ebug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
741 \details Sets the priority of a device specific interrupt or a processor exception.
743 or negative to specify a processor exception.
746 \note The priority cannot be set for every processor exception.
765 \details Reads the priority of a device specific interrupt or a processor exception.
767 or negative to specify a processor exception.
842 or negative to specify a processor exception.
859 or negative to specify a processor exception.
Dcore_cm1.h187 \brief Type definitions and defines for Cortex-M processor based devices.
520 …ebug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
768 \details Sets the priority of a device specific interrupt or a processor exception.
770 or negative to specify a processor exception.
773 \note The priority cannot be set for every processor exception.
792 \details Reads the priority of a device specific interrupt or a processor exception.
794 or negative to specify a processor exception.
869 or negative to specify a processor exception.
886 or negative to specify a processor exception.
Dcore_sc000.h198 \brief Type definitions and defines for Cortex-M processor based devices.
624 …ebug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
874 \details Sets the priority of a device specific interrupt or a processor exception.
876 or negative to specify a processor exception.
879 \note The priority cannot be set for every processor exception.
898 \details Reads the priority of a device specific interrupt or a processor exception.
900 or negative to specify a processor exception.
923 or negative to specify a processor exception.
940 or negative to specify a processor exception.
Dcore_cm0plus.h198 \brief Type definitions and defines for Cortex-M processor based devices.
608 …ebug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
859 \details Sets the priority of a device specific interrupt or a processor exception.
861 or negative to specify a processor exception.
864 \note The priority cannot be set for every processor exception.
883 \details Reads the priority of a device specific interrupt or a processor exception.
885 or negative to specify a processor exception.
960 or negative to specify a processor exception.
983 or negative to specify a processor exception.
/cmsis_6-latest/CMSIS/RTOS2/Include/
Dcmsis_os2.h27 * Added provisional support for processor affinity in SMP systems:
221 // Thread processor affinity (affinity_mask in \ref osThreadAttr_t).
222 #define osThreadProcessor(n) (1UL << (n)) ///< Thread processor number for SMP systems
296 …uint32_t affinity_mask; ///< processor affinity mask for binding the thread to a CPU…
534 /// Set processor affinity mask of a thread.
536 /// \param[in] affinity_mask processor affinity mask for the thread.
540 /// Get current processor affinity mask of a thread.
542 /// \return current processor affinity mask of the specified thread.

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