1/** 2\defgroup NVIC_gr Interrupts and Exceptions (NVIC) 3@{ 4\brief Functions to access the Nested Vector Interrupt Controller (NVIC). 5\details 6This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC). 7 8Arm provides a template file <strong>startup_<em>device</em></strong> for each supported 9compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific 10interrupt handlers. Each interrupt handler is defined as a <strong><em>weak</em></strong> function 11to an dummy handler. These interrupt handlers can be used directly in application software 12without being adapted by the programmer. 13 14The table below lists the core exception vectors of the various Cortex-M processors. 15 16<table class="cmtable" summary="Core Exception Name"> 17 <tr> 18 <th>Exception Vector</th> 19 <th>Handler Function</th> 20 <th>IRQn<br/>Value</th> 21 <th title="Cortex-M0/M0+ 22\if ARMSC 23and SC000 24\endif 25 ">Armv6-M</th> 26 <th title="Cortex-M3/M4/M7 27\if ARMSC 28and SC300 29\endif 30 ">Armv7-M</th> 31\if ARMv8M 32 <th title="Cortex-M23">Armv8-M<br/>Baseline</th> 33 <th title="Cortex-M33/M35P">Armv8-M<br/>Mainline</th> 34 <th>Armv8.1-M<br/>Mainline</th> 35\endif 36 <th>Description</th> 37 </tr> 38 <tr> 39 <td><b>NonMaskableInt_IRQn</b></td> 40 <td>NMI_Handler</td> 41 <td>-14</td> 42 <td><center>√</center></td> 43 <td><center>√</center></td> 44\if ARMv8M 45 <td><center>√</center></td> 46 <td><center>√</center></td> 47 <td><center>√</center></td> 48\endif 49 <td>Non Maskable Interrupt</td> 50 </tr> 51 <tr> 52 <td><b>HardFault_IRQn</b></td> 53 <td>HardFault_Handler</td> 54 <td>-13</td> 55 <td><center>√</center></td> 56 <td><center>√</center></td> 57\if ARMv8M 58 <td><center>√</center></td> 59 <td><center>√</center></td> 60 <td><center>√</center></td> 61\endif 62 <td>Hard Fault Interrupt</td> 63 </tr> 64 <tr> 65 <td><b>MemoryManagement_IRQn</b></td> 66 <td>MemManage_Handler</td> 67 <td>-12</td> 68 <td><center>—</center></td> 69 <td><center>√</center></td> 70\if ARMv8M 71 <td><center>—</center></td> 72 <td><center>√</center></td> 73 <td><center>√</center></td> 74\endif 75 <td>Memory Management Interrupt</td> 76 </tr> 77 <tr> 78 <td><b>BusFault_IRQn</b></td> 79 <td>BusFault_Handler</td> 80 <td>-11</td> 81 <td><center>—</center></td> 82 <td><center>√</center></td> 83\if ARMv8M 84 <td><center>—</center></td> 85 <td><center>√</center></td> 86 <td><center>√</center></td> 87\endif 88 <td>Bus Fault Interrupt</td> 89 </tr> 90 <tr> 91 <td><b>UsageFault_IRQn</b></td> 92 <td>UsageFault_Handler</td> 93 <td>-10</td> 94 <td><center>—</center></td> 95 <td><center>√</center></td> 96\if ARMv8M 97 <td><center>—</center></td> 98 <td><center>√</center></td> 99 <td><center>√</center></td> 100\endif 101 <td>Usage Fault Interrupt</td> 102 </tr> 103\if ARMv8M 104 <tr> 105 <td><b>SecureFault_IRQn</b></td> 106 <td>SecureFault_Handler</td> 107 <td>-9</td> 108 <td><center>—</center></td> 109 <td><center>—</center></td> 110 <td><center>√</center></td> 111 <td><center>√</center></td> 112 <td><center>√</center></td> 113 <td>Secure Fault Interrupt</td> 114 </tr> 115\endif 116 <tr> 117 <td><b>SVCall_IRQn</b></td> 118 <td>SVC_Handler</td> 119 <td>-5</td> 120 <td><center>√</center></td> 121 <td><center>√</center></td> 122\if ARMv8M 123 <td><center>√</center></td> 124 <td><center>√</center></td> 125 <td><center>√</center></td> 126\endif 127 <td>SVC Interrupt </td> 128 </tr> 129 <tr> 130 <td><b>DebugMonitor_IRQn</b></td> 131 <td>DebugMon_Handler</td> 132 <td>-4</td> 133 <td><center>—</center></td> 134 <td><center>√</center></td> 135\if ARMv8M 136 <td><center>—</center></td> 137 <td><center>√</center></td> 138 <td><center>√</center></td> 139\endif 140 <td>Debug Monitor Interrupt</td> 141 </tr> 142 <tr> 143 <td><b>PendSV_IRQn</b></td> 144 <td>PendSV_Handler</td> 145 <td>-2</td> 146 <td><center>√</center></td> 147 <td><center>√</center></td> 148\if ARMv8M 149 <td><center>√</center></td> 150 <td><center>√</center></td> 151 <td><center>√</center></td> 152\endif 153 <td>Pend SV Interrupt</td> 154 </tr> 155 <tr> 156 <td><b>SysTick_IRQn</b></td> 157 <td>SysTick_Handler</td> 158 <td>-1</td> 159 <td><center>√</center></td> 160 <td><center>√</center></td> 161\if ARMv8M 162 <td><center>√</center></td> 163 <td><center>√</center></td> 164 <td><center>√</center></td> 165\endif 166 <td>System Tick Interrupt</td> 167 </tr> 168</table> 169 170 171Vector Table 172============ 173The Vector Table defines the entry addresses of the processor exceptions and the 174device specific interrupts. It is typically located at the beginning of the 175program memory, however \ref using_vtor it can be relocated to RAM. The symbol 176<b>__Vectors</b> is the address of the vector table in the startup code and the 177register <b>SCB->VTOR</b> holds the start address of the vector table. 178 179\if ARMv8M 180An Armv8-M implementation with TrustZone provides two vector tables: 181 - vector table for Secure handlers 182 - vector table for Non-Secure handlers 183 184Refer to \ref Model_TrustZone for more information. 185\endif 186 187Processor Exceptions 188-------------------- 189At the beginning of the vector table, the initial stack value and the 190exception vectors of the processor are defined. The vector table below 191shows the exception vectors of a Armv8-M Mainline processor. Other processor 192variants may have fewer vectors. 193 194\code 195__Vectors DCD __initial_sp ; Top of Stack initialization 196 DCD Reset_Handler ; Reset Handler 197 DCD NMI_Handler ; NMI Handler 198 DCD HardFault_Handler ; Hard Fault Handler 199 DCD MemManage_Handler ; MPU Fault Handler 200 DCD BusFault_Handler ; Bus Fault Handler 201 DCD UsageFault_Handler ; Usage Fault Handler 202 DCD SecureFault_Handler ; Secure Fault Handler 203 DCD 0 ; Reserved 204 DCD 0 ; Reserved 205 DCD 0 ; Reserved 206 DCD SVC_Handler ; SVC Handler 207 DCD DebugMon_Handler ; Debug Monitor Handler 208 DCD 0 ; Reserved 209 DCD PendSV_Handler ; PendSV Handler 210 DCD SysTick_Handler ; SysTick Handler 211\endcode 212 213 214Device Specific Vectors 215----------------------- 216Following the processor exception vectors, the vector table contains also the 217device specific interrupt vectors. 218 219\code 220; device specific interrupts 221 DCD WWDG_IRQHandler ; Window Watchdog 222 DCD PVD_IRQHandler ; PVD through EXTI Line detect 223 DCD TAMPER_IRQHandler ; Tamper 224\endcode 225 226All device specific interrupts should have a default interrupt handler function that can 227be overwritten in user code. Below is an example for this default handler function. 228 229\code 230Default_Handler PROC 231 EXPORT WWDG_IRQHandler [WEAK] 232 EXPORT PVD_IRQHandler [WEAK] 233 EXPORT TAMPER_IRQHandler [WEAK] 234 : 235 : 236 WWDG_IRQHandler 237 PVD_IRQHandler 238 TAMPER_IRQHandler 239 : 240 : 241 B . 242 ENDP 243\endcode 244 245 246The user application may simply define an interrupt handler function by using the handler name 247as shown below. 248 249\code 250void WWDG_IRQHandler(void) 251{ 252 ... 253} 254\endcode 255 256NVIC Function Usage 257=================== 258The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device. 259 260Code Example 1 261-------------- 262\code 263#include "LPC17xx.h" 264 265uint32_t priorityGroup; /* Variables to store priority group and priority*/ 266uint32_t priority; 267uint32_t preemptPriority; 268uint32_t subPriority; 269 270int main (void) { 271 NVIC_SetPriorityGrouping(5); /* Set priority group to 5: 272 Bit[7..6] preempt priority Bits, 273 Bit[5..3] subpriority Bits 274 (valid for five priority bits)*/ 275 276 priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping*/ 277 278 priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority 279 Note: priority depends on the used priority grouping*/ 280 NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority*/ 281 282 priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again*/ 283 NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority); 284 285 while(1); 286} 287\endcode 288 289 290Code Example 2 291-------------- 292\code 293#include "LPC17xx.h" 294 295uint32_t active; /* Variable to store interrupt active state*/ 296 297void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */ 298 299 if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occurred*/ 300 LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occurred*/ 301 } 302 active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0*/ 303} 304 305int main (void) { 306 /* Set match channel register MR0 to 1 millisecond*/ 307 LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms?*/ 308 309 LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0*/ 310 NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0*/ 311 LPC_TIM0->TCR = (1 << 0); /* Enable timer 0*/ 312 313 while(1); 314} 315\endcode 316 317 318NVIC API Virtualization 319======================= 320The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing 321secure systems that control access to peripherals and related interrupts. 322These overrides allow an operating system to control the access privileges of 323application code to critical interrupts. 324 325The NVIC function virtualization is enabled with the following \#define symbols: 326 - \ref CMSIS_NVIC_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) NVIC functions. 327 - \ref CMSIS_VECTAB_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions. 328 329*/ 330 331#define CMSIS_NVIC_VIRTUAL ///< Virtualization of the NVIC API 332/** 333\def CMSIS_NVIC_VIRTUAL 334When \ref CMSIS_NVIC_VIRTUAL is defined, the NVIC access functions in the table below must be implemented 335for virtualizing NVIC access. These functions should be implemented 336in a separate source module. 337The original CMSIS-Core __NVIC functions are always available independent of \ref CMSIS_NVIC_VIRTUAL. 338 339NVIC Access Functions | CMSIS-Core Functions 340--------------------------|--------------------------------------------- 341NVIC_EnableIRQ | __NVIC_EnableIRQ 342NVIC_GetEnableIRQ | __NVIC_GetEnableIRQ 343NVIC_DisableIRQ | __NVIC_DisableIRQ 344NVIC_GetPendingIRQ | __NVIC_GetPendingIRQ 345NVIC_SetPendingIRQ | __NVIC_SetPendingIRQ 346NVIC_ClearPendingIRQ | __NVIC_ClearPendingIRQ 347NVIC_GetActive | __NVIC_GetActive 348NVIC_SetPriority | __NVIC_SetPriority 349NVIC_GetPriority | __NVIC_GetPriority 350NVIC_SetPriorityGrouping | __NVIC_SetPriorityGrouping 351NVIC_GetPriorityGrouping | __NVIC_GetPriorityGrouping 352*/ 353 354#define CMSIS_VECTAB_VIRTUAL ///< Virtualization of interrupt vector table access functions 355/** 356 357\def CMSIS_VECTAB_VIRTUAL 358When \ref CMSIS_NVIC_VIRTUAL is defined, the functions in the table below must be replaced 359to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented 360in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update. 361 362The original CMSIS-Core functions are always available, but prefixed with __NVIC. 363 364Interrupt Vector Table Access | CMSIS-Core Functions 365-------------------------------|--------------------------------------------- 366NVIC_GetVector | __NVIC_GetVector 367NVIC_SetVector | __NVIC_SetVector 368 369*/ 370 371 372/**************************************************************************************************/ 373/** \brief Definition of IRQn numbers 374 375 376The core exception enumeration names for IRQn values are defined in the \ref device_h_pg. 377 378 - Negative IRQn values represent processor core exceptions (internal interrupts). 379 - Positive IRQn values represent device-specific exceptions (external interrupts). 380 - The first device-specific interrupt has the IRQn value 0. 381 382The table below describes the core exception names and their availability in various Cortex-M cores. 383*/ 384typedef enum IRQn 385{ 386/****** Cortex-M3 Processor Exceptions/Interrupt Numbers **************************/ 387 NonMaskableInt_IRQn = -14, ///< Exception 2: Non Maskable Interrupt 388 HardFault_IRQn = -13, ///< Exception 3: Hard Fault Interrupt 389 MemoryManagement_IRQn = -12, ///< Exception 4: Memory Management Interrupt [not on Cortex-M0 variants] 390 BusFault_IRQn = -11, ///< Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants] 391 UsageFault_IRQn = -10, ///< Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants] 392\if ARMv8M 393 SecureFault_IRQn = -9, ///< Exception 7: Secure Fault Interrupt [only on Armv8-M] 394\endif 395 SVCall_IRQn = -5, ///< Exception 11: SVC Interrupt 396 DebugMonitor_IRQn = -4, ///< Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants] 397 PendSV_IRQn = -2, ///< Exception 14: Pend SV Interrupt [not on Cortex-M0 variants] 398 SysTick_IRQn = -1, ///< Exception 15: System Tick Interrupt 399/****** Device-specific Interrupt Numbers *****************************************/ 400 WWDG_STM_IRQn = 0, ///< Device Interrupt 0: Window WatchDog Interrupt 401 PVD_STM_IRQn = 1, ///< Device Interrupt 1: PVD through EXTI Line detection Interrupt 402 } IRQn_Type; 403 404/**************************************************************************************************/ 405/** \brief Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000] 406 407 The function sets the priority grouping \em PriorityGroup using the required unlock sequence. 408 \em PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field 409 determines the split of group priority from subpriority. 410 Only values from 0..7 are used. 411 In case of a conflict between priority grouping and available 412 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 413 414 \param [in] PriorityGroup Priority group 415 416 \remarks 417 - not for Cortex-M0, Cortex-M0+, or SC000. 418 - By default, priority group setting is zero. 419 420 \sa 421 - \ref NVIC_GetPriorityGrouping; NVIC_SetPriority; SCB_Type 422 - \ref ref_man_sec "Cortex-M Generic User Guides" 423*/ 424void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 425 426 427/**************************************************************************************************/ 428/** 429 \brief Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000] 430 431 This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]). 432 433 \return Priority grouping field 434 435 \remarks 436 - not for Cortex-M0, Cortex-M0+, or SC000. 437 - By default, priority group setting is zero. 438 439 \sa 440 - \ref NVIC_SetPriorityGrouping; NVIC_GetPriority; SCB_Type 441 - \ref ref_man_sec "Cortex-M Generic User Guides" 442 443*/ 444uint32_t NVIC_GetPriorityGrouping(void); 445 446 447/**************************************************************************************************/ 448/** 449 \brief Enable a device specific interrupt 450 451 This function enables the specified device specific interrupt \em IRQn. 452 \em IRQn cannot be a negative value. 453 454 \param [in] IRQn Interrupt number 455 456 \remarks 457 - IRQn must not be negative. 458 - The registers that control the enabling and disabling of interrupts are called 459 SETENA and CLRENA. 460 - The number of supported interrupts depends on the implementation of the chip designer 461 and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: 462 \n ICTR[4:0] 463 - 0 - 32 interrupts supported 464 - 1 - 64 interrupts supported 465 - ... 466 467 \sa 468 - \ref NVIC_DisableIRQ; SCnSCB_Type; 469 - \ref ref_man_sec "Cortex-M Generic User Guides" 470*/ 471void NVIC_EnableIRQ(IRQn_Type IRQn); 472 473 474/**************************************************************************************************/ 475/** 476 \brief Get a device specific interrupt enable status 477 478 This function returns the interrupt enable status for the specified device specific interrupt \em IRQn. 479 \em IRQn cannot be a negative value. 480 481 \param [in] IRQn Interrupt number 482 483 \returns 484 - 0 Interrupt is not enabled 485 - 1 Interrupt is enabled 486 487 \remarks 488 - IRQn must not be negative. 489 - The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA. 490 491 \sa 492 - \ref NVIC_EnableIRQ; NVIC_DisableIRQ; 493 - \ref ref_man_sec "Cortex-M Generic User Guides" 494*/ 495uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn); 496 497 498/**************************************************************************************************/ 499/** 500 \brief Disable a device specific interrupt 501 502 This function disables the specified device specific interrupt \em IRQn. 503 \em IRQn cannot be a negative value. 504 505 \param [in] IRQn Number of the external interrupt to disable 506 507 \remarks 508 - IRQn must not be negative. 509 - The registers that control the enabling and disabling of interrupts are called 510 SETENA and CLRENA. 511 512 \sa 513 - \ref NVIC_EnableIRQ 514 - \ref ref_man_sec "Cortex-M Generic User Guides" 515*/ 516void NVIC_DisableIRQ(IRQn_Type IRQn); 517 518 519/**************************************************************************************************/ 520/** 521 \brief Get the pending device specific interrupt 522 523 This function returns the pending status of the specified device specific interrupt \em IRQn. 524 525 \param [in] IRQn Interrupt number 526 527 \returns 528 - 0 Interrupt is not pending 529 - 1 Interrupt is pending 530 531 \remarks 532 - IRQn must not be negative. 533 - The registers that control the status of interrupts are called SETPEND and CLRPEND. 534 535 \sa 536 - \ref NVIC_SetPendingIRQ; NVIC_ClearPendingIRQ 537 - \ref ref_man_sec "Cortex-M Generic User Guides" 538*/ 539uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); 540 541 542/**************************************************************************************************/ 543/** 544 \brief Set a device specific interrupt to pending 545 546 This function sets the pending bit for the specified device specific interrupt \em IRQn. 547 \em IRQn cannot be a negative value. 548 549 \param [in] IRQn Interrupt number 550 551 \remarks 552 - IRQn must not be negative. 553 - The registers that control the status of interrupts are called SETPEND and CLRPEND. 554 555 \sa 556 - \ref NVIC_GetPendingIRQ; NVIC_ClearPendingIRQ 557 - \ref ref_man_sec "Cortex-M Generic User Guides" 558*/ 559void NVIC_SetPendingIRQ(IRQn_Type IRQn); 560 561 562/**************************************************************************************************/ 563/** 564 \brief Clear a device specific interrupt from pending 565 566 This function removes the pending state of the specified device specific interrupt \em IRQn. 567 \em IRQn cannot be a negative number. 568 569 \param [in] IRQn Interrupt number 570 571 \remarks 572 - IRQn must not be negative. 573 - The registers that control the status of interrupts are called SETPEND and CLRPEND. 574 - An interrupt can have the status pending though it is not active. 575 576 \sa 577 - \ref NVIC_SetPendingIRQ; NVIC_GetPendingIRQ 578 - \ref ref_man_sec "Cortex-M Generic User Guides" 579*/ 580void NVIC_ClearPendingIRQ(IRQn_Type IRQn); 581 582 583/**************************************************************************************************/ 584/** 585 \brief Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000] 586 587 This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and 588 returns the active bit of the interrupt \em IRQn. 589 590 \param [in] IRQn Interrupt number 591 592 \returns 593 - 0 Interrupt is not active 594 - 1 Interrupt is active, or active and pending 595 596 \remarks 597 - not for Cortex-M0, Cortex-M0+, or SC000. 598 - IRQn must not be negative. 599 - Each external interrupt has an active status bit. When the processor starts the interrupt 600 handler the bit is set to 1 and cleared when the interrupt return is executed. 601 - When an ISR is preempted and the processor executes another interrupt handler, the 602 previous interrupt is still defined as active. 603 604 \sa 605 - \ref ref_man_sec "Cortex-M Generic User Guides" 606 607*/ 608uint32_t NVIC_GetActive(IRQn_Type IRQn); 609 610 611/**************************************************************************************************/ 612/** 613 \brief Set the priority for an interrupt 614 615 Sets the priority for the interrupt specified by \em IRQn.\em IRQn can can specify any 616 device specific interrupt, or processor exception. The \em priority specifies 617 the interrupt priority value, whereby lower values indicate a higher priority. The default 618 priority is 0 for every interrupt. This is the highest possible priority. 619 620 The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) 621 priority that is higher than any configurable exception or interrupt. 622 623 \param [in] IRQn Interrupt Number 624 \param [in] priority Priority to set 625 626 \remarks 627 - The number of priority levels is configurable and depends on the implementation of the 628 chip designer. To determine the number of bits implemented for interrupt priority-level 629 registers, write \em 0xFF to one of the priority-level register, then read back the value. For 630 example, if the minimum number of 3 bits have been implemented, the read-back value is \em 0xE0. 631 - Writes to unimplemented bits are ignored. 632 - <b>For Cortex-M0</b>: 633 - Dynamic switching of interrupt priority levels is not supported. The priority level of 634 an interrupt should not be changed after it has been enabled. 635 - Supports 0 to 192 priority levels. 636 - Priority-level registers are 2 bit wide, occupying the two MSBs. 637 Each Interrupt Priority Level Register is 1-byte wide. 638 - <b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>: 639 - Dynamic switching of interrupt priority levels is supported. 640 - Supports 0 to 255 priority levels. 641 - Priority-level registers have a maximum width of 8 bits and a minimum of 3 bits. 642 Each register can be further divided into preempt priority level and subpriority level. 643 644 \sa 645 - \ref NVIC_GetPriority; NVIC_SetPriorityGrouping; __set_BASEPRI; 646 - \ref ref_man_sec "Cortex-M Generic User Guides" 647*/ 648void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); 649 650 651/**************************************************************************************************/ 652/** 653 \brief Get the priority of an interrupt 654 655 This function reads the priority for the specified interrupt \em IRQn. \em IRQn can can specify 656 any device specific interrupt, or processor exception. 657 658 The returned priority value is automatically aligned to the implemented 659 priority bits of the microcontroller. 660 661 \param [in] IRQn Interrupt number 662 663 \returns Interrupt priority 664 665 \remarks 666 - Each external interrupt has an associated priority-level register. 667 - Unimplemented bits are read as zero. 668 669 \sa 670 - \ref NVIC_SetPriority; NVIC_GetPriorityGrouping; __get_BASEPRI; 671 - \ref ref_man_sec "Cortex-M Generic User Guides" 672*/ 673uint32_t NVIC_GetPriority(IRQn_Type IRQn); 674 675 676/**************************************************************************************************/ 677/** 678 \brief Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000] 679 680 This function encodes the priority for an interrupt with the priority group \em PriorityGroup, 681 preemptive priority value \em PreemptPriority, and subpriority value \em SubPriority. 682 In case of a conflict between priority grouping and available 683 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 684 685 \param [in] PriorityGroup Priority group 686 \param [in] PreemptPriority Preemptive priority value (starting from 0) 687 \param [in] SubPriority Subpriority value (starting from 0) 688 689 \returns Encoded priority for the interrupt 690 691 692 \remarks 693 - not for Cortex-M0, Cortex-M0+, or SC000. 694 695 \sa 696 - \ref NVIC_DecodePriority; NVIC_SetPriority; 697 - \ref ref_man_sec "Cortex-M Generic User Guides" 698*/ 699uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); 700 701 702/**************************************************************************************************/ 703/** 704 \brief Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000] 705 706 This function decodes an interrupt priority value with the priority group \em PriorityGroup to 707 preemptive priority value \em pPreemptPriority and subpriority value \em pSubPriority. 708 In case of a conflict between priority grouping and available 709 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 710 711 \param [in] Priority Priority 712 \param [in] PriorityGroup Priority group 713 \param [out] *pPreemptPriority Preemptive priority value (starting from 0) 714 \param [out] *pSubPriority Subpriority value (starting from 0) 715 716 717 \remarks 718 - not for Cortex-M0, Cortex-M0+, or SC000. 719 720 \sa 721 - \ref NVIC_EncodePriority; NVIC_GetPriority; NVIC_GetPriorityGrouping; 722 - \ref ref_man_sec "Cortex-M Generic User Guides" 723*/ 724void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 725 726 727/**************************************************************************************************/ 728/** 729 \brief Read Interrupt Vector [not for Cortex-M0, SC000] 730 731 This function allows to read the address of an interrupt handler function. 732 733 \param [in] IRQn Interrupt number 734 735 \returns Address of interrupt handler function 736 737 \remarks 738 - For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented. 739 740 \sa 741 - \ref NVIC_SetVector 742 - \ref ref_man_sec "Cortex-M Generic User Guides" 743*/ 744uint32_t NVIC_GetVector(IRQn_Type IRQn); 745 746 747/**************************************************************************************************/ 748/** 749 \brief Modify Interrupt Vector [not for Cortex-M0, SC000] 750 751 This function allows to change the address of an interrupt handler function. 752 753 \param [in] IRQn Interrupt number 754 \param [in] vector Address of new interrupt handler function 755 756 \remarks 757 - Usage of this function requires vector relocation to RAM. Refer to \ref using_vtor for more information. 758 - For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented. 759 760 \sa 761 - \ref NVIC_GetVector 762 - \ref ref_man_sec "Cortex-M Generic User Guides" 763*/ 764void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); 765 766 767/**************************************************************************************************/ 768/** 769 \brief Reset the system 770 771 This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register. 772 773 \remarks 774 - In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and 775 most parts of the system, but should not affect the debug system. 776 777 \sa 778 - \ref ref_man_sec "Cortex-M Generic User Guides" 779*/ 780void NVIC_SystemReset (void); 781 782/** 783\cond (ARMv8M) 784*/ 785/** 786 \brief Get Interrupt Target State 787 \details Reads the interrupt target field from the non-secure NVIC when in secure state. 788 \param [in] IRQn External interrupt number. Value cannot be negative. 789 \returns 790 - 0 if interrupt is assigned to Secure 791 - 1 if interrupt is assigned to Non Secure 792 \remarks 793 - Only available for Armv8-M in secure state. 794 795 \sa 796 - \ref NVIC_ClearTargetState; NVIC_SetTargetState; 797*/ 798uint32_t NVIC_GetTargetState(IRQn_Type IRQn); 799 800/** 801 \brief Set Interrupt Target State 802 \details Sets the interrupt target field in the non-secure NVIC when in secure state. 803 \param [in] IRQn External interrupt number. Value cannot be negative. 804 \returns 805 - 0 if interrupt is assigned to Secure 806 - 1 if interrupt is assigned to Non Secure 807 \remarks 808 - Only available for Armv8-M in secure state. 809 810 \sa 811 - \ref NVIC_ClearTargetState; NVIC_GetTargetState; 812*/ 813uint32_t NVIC_SetTargetState(IRQn_Type IRQn); 814 815/** 816 \brief Clear Interrupt Target State 817 \details Clears the interrupt target field in the non-secure NVIC when in secure state. 818 \param [in] IRQn External interrupt number. Value cannot be negative. 819 \returns 820 - 0 if interrupt is assigned to Secure 821 - 1 if interrupt is assigned to Non Secure 822 \remarks 823 - Only available for Armv8-M in secure state. 824 825 \sa 826 - \ref NVIC_GetTargetState; NVIC_SetTargetState; 827*/ 828uint32_t NVIC_ClearTargetState(IRQn_Type IRQn); 829 830/** \endcond*/ 831 832/** @} end of NVIC_gr*/ 833
