| /Zephyr-latest/tests/drivers/pinctrl/gd32/src/ |
| D | main_afio.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG); in ZTEST()
30 zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP); in ZTEST()
32 pin = scfg->pins[1]; in ZTEST()
33 zassert_equal(GD32_PORT_GET(pin), 1); in ZTEST()
34 zassert_equal(GD32_PIN_GET(pin), 1); in ZTEST()
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| D | main_af.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_AF_GET(pin), GD32_AF0); in ZTEST()
30 zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE); in ZTEST()
31 zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP); in ZTEST()
32 zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ); in ZTEST()
34 pin = scfg->pins[1]; in ZTEST()
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_gpio.h | 19 * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
62 /** Connect pin to peripheral A. */
64 /** Connect pin to peripheral B. */
66 /** Connect pin to peripheral C. */
68 /** Connect pin to peripheral D. */
70 /** Connect pin to peripheral E. */
72 /** Connect pin to peripheral F. */
74 /** Connect pin to peripheral G. */
76 /** Connect pin to peripheral H. */
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_ambiq.c | 12 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
17 pin_config.uFuncSel = pin->alt_func; in pinctrl_configure_pin()
19 pin->input_enable ? AM_HAL_GPIO_PIN_INPUT_ENABLE : AM_HAL_GPIO_PIN_INPUT_NONE; in pinctrl_configure_pin()
20 pin_config.eGPOutcfg = pin->push_pull ? AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL in pinctrl_configure_pin()
21 : pin->open_drain ? AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN in pinctrl_configure_pin()
22 : pin->tristate ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE in pinctrl_configure_pin()
24 pin_config.eDriveStrength = pin->drive_strength; in pinctrl_configure_pin()
25 pin_config.uNCE = pin->iom_nce; in pinctrl_configure_pin()
27 pin_config.bIomMSPIn = pin->iom_mspi; in pinctrl_configure_pin()
29 pin_config.uIOMnum = pin->iom_num; in pinctrl_configure_pin()
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| D | pinctrl_rpi_pico.c | 12 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
14 gpio_init(pin->pin_num); in pinctrl_configure_pin()
15 gpio_set_function(pin->pin_num, pin->alt_func); in pinctrl_configure_pin()
16 gpio_set_pulls(pin->pin_num, pin->pullup, pin->pulldown); in pinctrl_configure_pin()
17 gpio_set_drive_strength(pin->pin_num, pin->drive_strength); in pinctrl_configure_pin()
18 gpio_set_slew_rate(pin->pin_num, (pin->slew_rate ? in pinctrl_configure_pin()
20 gpio_set_input_hysteresis_enabled(pin->pin_num, pin->schmitt_enable); in pinctrl_configure_pin()
21 gpio_set_input_enabled(pin->pin_num, pin->input_enable); in pinctrl_configure_pin()
22 gpio_set_oeover(pin->pin_num, pin->oe_override); in pinctrl_configure_pin()
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| D | pinctrl_numicro.c | 15 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
16 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
17 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
18 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
19 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
21 #define SLEWCTL_PIN_SHIFT(pin) ((pin) * 2) argument
22 #define SLEWCTL_MASK(pin) (3 << SLEWCTL_PIN_SHIFT(pin)) argument
26 #define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \ argument
28 ((pin) > 7 ? 4 : 0)))
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| D | pinctrl_eos_s3.c | 34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
63 static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_eos_s3_configure_pin() argument
68 reg_value |= (pin->iof & PAD_FUNC_SEL_MASK); in pinctrl_eos_s3_configure_pin()
71 WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1); in pinctrl_eos_s3_configure_pin()
74 WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable); in pinctrl_eos_s3_configure_pin()
75 WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate); in pinctrl_eos_s3_configure_pin()
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| /Zephyr-latest/drivers/pinctrl/renesas/rz/ |
| D | pinctrl_rzt2m.c | 21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
32 #define PFC_FUNC_MASK(pin) (0xf << (pin * 4)) argument
34 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
41 sys_write8(rselp | BIT(pin->pin), RSELP(pin->port)); in pinctrl_configure_pin()
43 pin->drive_strength, (pin->pull_up == 1 ? 1U : (pin->pull_down == 1 ? 2U : 0)), in pinctrl_configure_pin()
44 pin->schmitt_enable, pin->slew_rate), in pinctrl_configure_pin()
45 DRCTL(pin->port, pin->pin)); in pinctrl_configure_pin()
[all …]
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | silabs,gecko-ethernet.yaml | 42 description: PHY MDC individual pin configuration defined as <location port pin>
47 description: PHY MDIO individual pin configuration defined as <location port pin>
53 description: Reference clock individual pin configuration defined as <location port pin>
58 description: Receive data valid individual pin configuration defined as <location port pin>
63 description: Transmit data 0 individual pin configuration defined as <location port pin>
68 description: Transmit data 1 individual pin configuration defined as <location port pin>
73 description: Transmit enable individual pin configuration defined as <location port pin>
78 description: Receive data 0 individual pin configuration defined as <location port pin>
83 description: Receive data 1 individual pin configuration defined as <location port pin>
88 description: Receive error individual pin configuration defined as <location port pin>
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | nxp_pint.h | 8 * @brief Driver for Pin interrupt and pattern match engine in NXP MCUs
10 * The Pin interrupt and pattern match engine (PINT) supports
13 * Pin inputs can generate separate interrupts to the NVIC, or be combined
15 * This driver currently only supports the pin interrupt feature of
25 * @brief Pin interrupt sources
27 * Pin interrupt sources available for use.
30 /* Do not generate Pin Interrupt */
32 /* Generate Pin Interrupt on rising edge */
34 /* Generate Pin Interrupt on falling edge */
36 /* Generate Pin Interrupt on both edges */
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| D | intc_xmc4xxx.h | 11 * @brief Enable interrupt for specific port_id and pin combination
14 * @param pin pin Pin the port
21 * @retval -ENOTSUP If the specific port_id/pin combination is not supported or
23 * @retval -EBUSY If the interrupt line is already used by a different port_id/pin
28 int intc_xmc4xxx_gpio_enable_interrupt(int port_id, int pin, enum gpio_int_mode mode,
32 * @brief Disable interrupt for specific port_id and pin combination
35 * @param pin pin Pin the port
37 * @retval -EINVAL If the specific port_id and pin combination has no interrupt
41 int intc_xmc4xxx_gpio_disable_interrupt(int port_id, int pin);
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| D | sam0_eic.h | 33 * @brief Acquire an EIC interrupt for specific port and pin combination
35 * This acquires the EIC interrupt for a specific port and pin combination,
41 * @param pin pin in the port
47 int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
51 * @brief Release the EIC interrupt for a specific port and pin combination
53 * Release the EIC configuration for a specific port and pin combination.
58 * @param pin pin in the port
60 int sam0_eic_release(int port, int pin);
63 * @brief Enable the EIC interrupt for a specific port and pin combination
66 * @param pin pin in the port
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| /Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/src/ |
| D | test_config.c | 16 unsigned int pin, in pin_get_raw_and_verify() argument
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
23 "Test point %d: failed to get pin value", idx); in pin_get_raw_and_verify()
25 "Test point %d: invalid pin get value", idx); in pin_get_raw_and_verify()
29 unsigned int pin, in pin_set_raw_and_verify() argument
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
33 "Test point %d: failed to set pin value", idx); in pin_set_raw_and_verify()
39 * - Configure pin in in/out mode, verify that gpio_pin_set_raw /
40 * gpio_pin_get_raw operations change pin state.
41 * - Verify that GPIO_OUTPUT_HIGH flag is initializing the pin to high.
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| /Zephyr-latest/boards/renesas/rcar_h3ulcb/ |
| D | rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi | 11 pin = <PIN_TX2_A FUNC_TX2_A>;
15 pin = <PIN_RX2_A FUNC_RX2_A>;
19 pin = <PIN_SD0_CLK FUNC_SD0_CLK>;
24 pin = <PIN_SD0_CMD FUNC_SD0_CMD>;
29 pin = <PIN_SD0_DATA0 FUNC_SD0_DAT0>;
34 pin = <PIN_SD0_DATA1 FUNC_SD0_DAT1>;
39 pin = <PIN_SD0_DATA2 FUNC_SD0_DAT2>;
44 pin = <PIN_SD0_DATA3 FUNC_SD0_DAT3>;
49 pin = <PIN_SD0_CLK FUNC_SD0_CLK>;
54 pin = <PIN_SD0_CMD FUNC_SD0_CMD>;
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | sparkfun,micromod-gpio.yaml | 12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
34 - 05 -> G0/BUS0 PIN 40
35 - 06 -> G1/BUS1 PIN 42
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_port.h | 8 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
17 * Pin flags/attributes
46 /** Connect pin to peripheral A. */
48 /** Connect pin to peripheral B. */
50 /** Connect pin to peripheral C. */
52 /** Connect pin to peripheral D. */
54 /** Connect pin to peripheral E. */
56 /** Connect pin to peripheral F. */
58 /** Connect pin to peripheral G. */
60 /** Connect pin to peripheral H. */
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| D | soc_port.c | 9 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
16 int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func) in soc_port_pinmux_set() argument
18 bool is_odd = pin & 1; in soc_port_pinmux_set()
19 int idx = pin / 2U; in soc_port_pinmux_set()
22 * even numbered pin goes in the bits 0..3 and the odd in soc_port_pinmux_set()
23 * numbered pin in bits 4..7. in soc_port_pinmux_set()
30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
35 void soc_port_configure(const struct soc_port_pin *pin) in soc_port_configure() argument
37 PortGroup *pg = pin->regs; in soc_port_configure()
38 uint32_t flags = pin->flags; in soc_port_configure()
[all …]
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| /Zephyr-latest/dts/bindings/sdhc/ |
| D | espressif,esp32-sdhc-slot.yaml | 28 clk-pin:
31 Clock pin for ESP32 and SoC models with fixed pins for SDIO.
33 using pin control (pinctrl-0 field).
35 cmd-pin:
38 Command pin for ESP32 and SoC models with fixed pins for SDIO.
40 using pin control (pinctrl-0 field).
42 d0-pin:
45 Data 0 pin for ESP32 and SoC models with fixed pins for SDIO.
47 using pin control (pinctrl-0 field).
49 d1-pin:
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | cc13xx_cc26xx-pinctrl.h | 15 #define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
16 #define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
18 #define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
20 #define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
22 #define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
23 #define IOC_PORT_MCU_UART0_TX 0x00000010 /* MCU UART0 Transmit Pin */
24 #define IOC_PORT_MCU_UART0_CTS 0x00000011 /* MCU UART0 Clear To Send Pin */
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_nxp_pint.c | 25 uint8_t pin: 6; member
34 /* Tracks pint interrupt source selected for each pin */
37 #define PIN_TO_INPUT_MUX_CONNECTION(pin) \ argument
38 ((PINTSEL_PMUX_ID << PMUX_SHIFT) + (pin))
40 /* Attaches pin to PINT IRQ slot using INPUTMUX */
41 static void attach_pin_to_pint(uint8_t pin, uint8_t pint_slot) in attach_pin_to_pint() argument
46 * and a integer describing the GPIO pin. in attach_pin_to_pint()
49 PIN_TO_INPUT_MUX_CONNECTION(pin)); in attach_pin_to_pint()
60 * @param pin: pin to use as interrupt source
61 * 0-64, corresponding to GPIO0 pin 1 - GPIO1 pin 31)
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,port-pinctrl.yaml | 5 NXP PORT pinctrl node. This node will define pin configurations in pin
7 group within the pin configuration defines the pin configuration for a
8 peripheral, and each numbered subgroup in the pin group defines all the pins
23 If only the required properties are supplied, the pin configuration register
37 description: NXP PORT pin controller pin group
40 NXP PORT pin controller pin configuration node
55 Pin mux selections for this group. See the soc level pinctrl DTSI file
64 Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
65 0 DSE_0- low drive strength when pin is configured as output
66 1 DSE_1- high drive strength when pin is configured as output
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | nxp,mipi-dbi-flexio-lcdif.yaml | 23 enwr-pin:
27 Pin select for WR(8080 mode), EN(6800 mode).
29 rd-pin:
32 Pin select for RD(8080 mode), not used in 6800 mode.
34 data-pin-start:
38 Start index of the data pin.
44 CS Pin
45 GPIO to drive the CS pin.
51 RS Pin
52 GPIO to drive the RS pin.
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| /Zephyr-latest/tests/drivers/sensor/adltc2990/boards/ |
| D | native_sim.overlay | 13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
30 pin-v4-voltage-divider-resistors = <0 1>;
39 pin-v1-voltage-divider-resistors = <0 1>;
40 pin-v2-voltage-divider-resistors = <0 1>;
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| /Zephyr-latest/boards/renesas/rcar_salvator_xs/ |
| D | rcar_salvator_xs-pinctrl.dtsi | 11 pin = <PIN_TX2_A FUNC_TX2_A>;
15 pin = <PIN_RX2_A FUNC_RX2_A>;
19 pin = <PIN_SD2_CLK FUNC_SD2_CLK>;
24 pin = <PIN_SD2_CMD FUNC_SD2_CMD>;
29 pin = <PIN_SD2_DATA0 FUNC_SD2_DAT0>;
34 pin = <PIN_SD2_DATA1 FUNC_SD2_DAT1>;
39 pin = <PIN_SD2_DATA2 FUNC_SD2_DAT2>;
44 pin = <PIN_SD2_DATA3 FUNC_SD2_DAT3>;
49 pin = <PIN_SD1_DATA0 FUNC_SD2_DAT4>;
54 pin = <PIN_SD1_DATA1 FUNC_SD2_DAT5>;
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| /Zephyr-latest/boards/renesas/rcar_spider_s4/ |
| D | rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi | 11 pin = <PIN_HTX0 FUNC_HTX0>;
15 pin = <PIN_HRX0 FUNC_HRX0>;
19 pin = <PIN_MMC_SD_CLK FUNC_MMC_SD_CLK>;
24 pin = <PIN_MMC_SD_CMD FUNC_MMC_SD_CMD>;
29 pin = <PIN_MMC_SD_D0 FUNC_MMC_SD_D0>;
34 pin = <PIN_MMC_SD_D1 FUNC_MMC_SD_D1>;
39 pin = <PIN_MMC_SD_D2 FUNC_MMC_SD_D2>;
44 pin = <PIN_MMC_SD_D3 FUNC_MMC_SD_D3>;
49 pin = <PIN_MMC_D4 FUNC_MMC_D4>;
54 pin = <PIN_MMC_D5 FUNC_MMC_D5>;
[all …]
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