Lines Matching full:pin
5 NXP PORT pinctrl node. This node will define pin configurations in pin
7 group within the pin configuration defines the pin configuration for a
8 peripheral, and each numbered subgroup in the pin group defines all the pins
23 If only the required properties are supplied, the pin configuration register
37 description: NXP PORT pin controller pin group
40 NXP PORT pin controller pin configuration node
55 Pin mux selections for this group. See the soc level pinctrl DTSI file
64 Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
65 0 DSE_0- low drive strength when pin is configured as output
66 1 DSE_1- high drive strength when pin is configured as output
73 Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
74 0 SRE_0_fast- fast slew rate when pin is configured as output
75 1 SRE_1_slow- slow slew rate when pin is configured as output
79 Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.