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Searched +full:pin +full:- +full:lpsr (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx-iomuxc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 These options can then be used in a pinctrl node with the "nxp,mcux-rt-pinctrl"
8 compatible string to define pin groups.
13 compatible: "nxp,imx-iomuxc"
16 - name: base.yaml
22 child-binding:
23 description: MCUX RT pin mux option
29 An array of values defining the pin mux selection, in the following format:
33 input_reg: peripheral register that will direct peripheral signal to pin
35 cfg_reg: register that will configure pin pull, drive strength, and open drain
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Dnxp,imx7d-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
14 bias-pull-up: PE=1, PS=<bias-pull-up-value index>
15 bias-pull-down: PE=1, PS=0
16 input-schmitt-enable: HYS=1
17 slew-rate: SRE=<enum idx>
18 drive-strength: DSE=<enum idx>
19 input-enable: SION=1 (in SW_PAD_CTL_MUX register)
21 If only required properties are supplied, the pin will have the following
26 SRE=<slew-rate>,
27 DSE=<drive-strength>,
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/Zephyr-latest/drivers/gpio/
Dgpio_mcux_igpio.c4 * SPDX-License-Identifier: Apache-2.0
23 #define DEV_CFG(_dev) ((const struct mcux_igpio_config *)(_dev)->config)
24 #define DEV_DATA(_dev) ((struct mcux_igpio_data *)(_dev)->data)
52 gpio_pin_t pin, gpio_flags_t flags) in mcux_igpio_configure() argument
54 const struct mcux_igpio_config *config = dev->config; in mcux_igpio_configure()
58 int cfg_idx = pin, i; in mcux_igpio_configure()
60 /* Make sure pin is supported */ in mcux_igpio_configure()
61 if ((config->common.port_pin_mask & BIT(pin)) == 0) { in mcux_igpio_configure()
62 return -ENOTSUP; in mcux_igpio_configure()
65 /* Some SOCs have non-contiguous gpio pin layouts, account for this */ in mcux_igpio_configure()
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/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
34 * RT11xx has multiple types of register layouts defined for pin configuration
104 uint8_t lpsr_mux: 1; /* Is pinmux reg LPSR type */