Searched +full:num +full:- +full:dma +full:- +full:ch (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/boards/intel/socfpga/agilex5_socdk/ |
| D | intel_socfpga_agilex5_socdk.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "intel,socfpga-agilex5";
14 #address-cells = <1>;
15 #size-cells = <1>;
19 zephyr,shell-uart = &uart0;
28 compatible = "zephyr,sdmmc-disk";
29 disk-name = "SD";
36 current-speed = <115200>;
40 full-duplex-mode-en;
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | snps,dwcxgmac.yaml | 2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
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| /Zephyr-latest/drivers/dma/ |
| D | dma_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
44 #define DMA_INTF(dma) REG32(dma + 0x00UL) argument
45 #define DMA_INTC(dma) REG32(dma + 0x04UL) argument
46 #define DMA_CHCTL(dma, ch) REG32((dma + 0x08UL) + 0x14UL * (uint32_t)(ch)) argument
47 #define DMA_CHCNT(dma, ch) REG32((dma + 0x0CUL) + 0x14UL * (uint32_t)(ch)) argument
48 #define DMA_CHPADDR(dma, ch) REG32((dma + 0x10UL) + 0x14UL * (uint32_t)(ch)) argument
49 #define DMA_CHMADDR(dma, ch) REG32((dma + 0x14UL) + 0x14UL * (uint32_t)(ch)) argument
52 #define GD32_DMA_INTF(dma) DMA_INTF(dma) argument
53 #define GD32_DMA_INTC(dma) DMA_INTC(dma) argument
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_mcux_sai.c | 2 * Copyright 2021,2023-2024 NXP Semiconductor INC.
5 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/dma.h>
22 #include <zephyr/dt-bindings/clock/imx_ccm.h>
46 * SAI driver uses source_gather_en/dest_scatter_en feature of DMA, and relies
47 * on DMA driver managing circular list of DMA blocks. Like eDMA driver links
49 * Calling dma_reload() adds new DMA block to DMA channel already configured,
50 * into the DMA driver's circular list of blocks.
56 * application provided buffer is queued to in_queue until loaded to DMA.
57 * when DMA channel is idle, buffer is retrieved from in_queue and loaded
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