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/Zephyr-Core-3.5.0/tests/drivers/rtc/rtc_api/boards/
Dqemu_x86_64.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * The RTC IRQ is not routed to the IOAPIC if the legacy
9 * IRQ bit is set. The IRQ is required for alarm
13 no-legacy-irq;
Dqemu_x86.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * The RTC IRQ is not routed to the IOAPIC if the legacy
9 * IRQ bit is set. The IRQ is required for alarm
13 no-legacy-irq;
/Zephyr-Core-3.5.0/dts/bindings/timer/
Dintel,hpet.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: HPET (High-Precision Event Timer)
17 no-legacy-irq:
19 description: Do not set legacy IRQ bit
/Zephyr-Core-3.5.0/doc/kernel/services/smp/
Dsmp.rst8 "symmetric" in the sense that no specific CPU is treated specially by
12 No special application code needs to be written to take advantage of
26 non-Zephyr code).
54 on top of the pre-existing :c:struct:`atomic_` layer (itself usually
58 One important difference between IRQ locks and spinlocks is that the
65 re-acquire it or it will deadlock (it is perfectly legal to nest
71 recursive semantics above, spinlocks in single-CPU contexts produce
72 identical code to legacy IRQ locks. In fact the entirety of the
75 Legacy irq_lock() emulation
80 SMP systems with identical semantics to their legacy versions. They
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/Zephyr-Core-3.5.0/subsys/bluetooth/controller/
DKconfig.ll_sw_split3 # Copyright (c) 2016-2017 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
102 # Controller's Co-Operative high priority Rx thread stack size.
129 https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers
139 bool "Legacy AD Data backup"
143 Backup Legacy Advertising Data when switching to Legacy Directed or
145 Legacy Non-Directed Advertising mode.
147 Advertising or switch between Legacy and Extended Advertising.
157 zero-based numbering. When using with Zephyr host this option can be
244 bool "Run in-system unit tests"
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-1.7.rst9 interfaces. This is the last release that will support the deprecated legacy
10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
12 This release introduces a new native IP stack, replacing the legacy uIP stack,
13 maintaining the legacy functionality, adding additional capabilities, and allowing
36 a legacy option to enable/disable legacy APIs. (using legacy.h)
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
72 This version removes the legacy uIP stack and introduces a new native IP stack.
74 will support the same functionality as the legacy IP stack found in 1.6, and
80 enabled simultaneously. No routing functionality is provided by IP stack
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Drelease-notes-1.6.rst7 release introduces the unified Kernel replacing the separate nano- and
8 micro-kernels and simplifying the overall Zephyr architecture and programming
10 Support for the ARM Cortex-M0/M0+ family was added and board support for
11 Cortex-M was expanded.
18 * The legacy API is still supported but deprecated.
19 * Legacy tests and samples were moved to tests/legacy and samples/legacy.
20 * Unified kernel documentation was added and legacy nanokernel/microkernel
22 * Added support for several ARM Cortex-M boards
34 * Added DLIST to operate in all elements of a doubly-linked list.
52 * ARM: Added support for ARM Cortex-M0/M0+.
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Drelease-notes-1.11.rst12 * Thread-level memory protection on x86, ARC and Arm, userspace and memory
15 * Initial Armv8-M architecture support.
20 * Firmware over-the-air (FOTA) updates over BLE using MCUmgr.
32 * SMP-aware scheduler
47 * Armv8-M initial architecture support, including the following cores:
49 * Arm Cortex-M23
50 * Arm Cortex-M33
74 * Refactored dts.fixup so common SoC-related fixes are in arch/<*>/soc
75 and board dts.fixup is only used for board-specific items.
82 * Added I2C master, QSPI flash, and GPIO drivers for nios-II
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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Dmigration-guide-3.5.rst21 taking a ``void *mem`` pointer instead of a ``void **mem`` double-pointer.
37 * The default C library used on most targets has changed from the built-in
47 increase by 8-16 bytes.
68 * Picolibc removes the ``-ffreestanding`` compiler option. This allows
71 the Zephyr required type -- ``int main(void)``.
85 * ``zephyr,memory-region-mpu`` was renamed ``zephyr,memory-attr`` and its type
89 .. code-block:: none
91 - "RAM" -> <( DT_MEM_ARM(ATTR_MPU_RAM) )>
92 - "RAM_NOCACHE" -> <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>
93 - "FLASH" -> <( DT_MEM_ARM(ATTR_MPU_FLASH) )>
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Drelease-notes-2.2.rst18 * Fix CVE-2020-10028
19 * Fix CVE-2020-10060
20 * Fix CVE-2020-10063
21 * Fix CVE-2020-10066
32 * :github:`23494` - Bluetooth: LL/PAC/SLA/BV-01-C fails if Slave-initiated Feature Exchange is disa…
33 * :github:`23485` - BT: host: Service Change indication sent regardless of whether it is needed or …
34 * :github:`23482` - 2M PHY + DLE and timing calculations on an encrypted link are wrong
35 * :github:`23070` - Bluetooth: controller: Fix ticker implementation to avoid catch up
36 * :github:`22967` - Bluetooth: controller: ASSERTION FAIL on invalid packet sequence
37 * :github:`24183` - [v2.2] Bluetooth: controller: split: Regression slave latency during connection…
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Drelease-notes-2.5.rst27 * CVE-2021-3323: Under embargo until 2021-04-14
28 * CVE-2021-3321: Under embargo until 2021-04-14
29 * CVE-2021-3320: Under embargo until 2021-04-14
39 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
56 * Changed vcnl4040 dts binding default for property 'proximity-trigger'.
63 * The :c:func:`mqtt_keepalive_time_left` function now returns -1 if keep alive
67 timeout usage must use the new-style k_timeout_t type and not the
68 legacy/deprecated millisecond counts.
87 GPIO-only regulators a devicetree property ``supply-gpios`` is defined as a
101 * ARM Musca-A board and SoC support deprecated and planned to be removed in 2.6.0.
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Drelease-notes-1.13.rst16 * Support for IEEE 802.1AS-2011 generalized Precision Time Protocol (gPTP)
23 * Basic support for Arm TrustZone in Armv8-M
42 * arch: arm: implement ARMv8-M MPU driver
43 * irq: Fix irq_lock api usage
44 * arch: arm: macro API for defining non-secure entry functions
48 * arch: ARM: Change the march used by cortex-m0 and cortex-m0plus
50 * arch: arm: basic Arm TrustZone-M functionality for Cortex-M23 and Cortex-M33
51 * arch: arm: built-in stack protection using Armv8-M SPLIM registers
52 * arch: arm: API for using TT intrinsics in Secure/Non-Secure Armv8-M firmware
54 * arch: arm: Set Zero Latency IRQ to priority level zero
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/Zephyr-Core-3.5.0/drivers/timer/
Dhpet.c2 * Copyright (c) 2018-2021 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/irq.h>
15 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
25 * specific. The timers are implemented as a single up-counter with
39 * COUNTER_CLK_PERIOD is not in femtoseconds (1e-15 sec).
44 #define GCONF_LR BIT(1) /* legacy interrupt routing, */
116 * 32-bit of the General Capabilities and ID Register. This can
209 /* COUNTER_CLK_PERIOD (CLK_PERIOD_REG) is in femtoseconds (1e-15 sec) */
216 * has no "sense" cell.
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Dmchp_xec_rtos_timer.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/irq.h>
36 * system timer. It supports both legacy ("tickful") mode as well as
67 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
77 /* Mask off bits[31:28] of 32-bit count */
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()
136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
141 TIMER_REGS->CTRL = 0U; in timer_restart()
142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()
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/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dloapic.h1 /* loapic.h - public LOAPIC APIs */
6 * SPDX-License-Identifier: Apache-2.0
27 #define LOAPIC_ISR 0x100 /* In-service Reg */
65 extern void z_loapic_int_vec_set(unsigned int irq, unsigned int vector);
66 extern void z_loapic_irq_enable(unsigned int irq);
67 extern void z_loapic_irq_disable(unsigned int irq);
70 * @brief Read 64-bit value from the local APIC in x2APIC mode.
81 * @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
95 * Returns a 32-bit value read from the local APIC, using the access
97 * that 64-bit reads are only allowed in x2APIC mode and can only be
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/Zephyr-Core-3.5.0/drivers/espi/
Dhost_subs_npcx.c4 * SPDX-License-Identifier: Apache-2.0
13 * This file contains the drivers of NPCX Host Sub-Modules that serve as an
16 * +------------+
17 * | Serial |---> TXD
18 * +<--->| Port |<--- RXD
19 * | | |<--> ...
20 * | +------------+
21 * | +------------+ |
22 * +------------+ |<--->| KBC & PM |<--->|
23 * eSPI_CLK --->| eSPI Bus | | | Channels | |
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/Zephyr-Core-3.5.0/arch/x86/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
13 # CPU Families - the SoC configuration should select the right one.
64 # Configuration common to both IA32 and Intel64 sub-architectures.
68 bool "Run in 64-bit mode"
166 bool "Compiler-generated SSEx instructions for floating point math"
194 This value normally need to be page-aligned.
200 int "Number of IRQ lines"
204 This option specifies the number of IRQ lines in the system. It
206 is used to track the association between vectors and IRQ numbers.
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/Zephyr-Core-3.5.0/doc/connectivity/bluetooth/
Dbluetooth-ctlr-arch.rst1 .. _bluetooth-ctlr-arch:
27 * Software-based Link Layer implementation
107 Pre-emption of Active Event
133 - Event handle (0, 1) < Event preparation (2, 3) < Event/Rx done (4) < Tx
136 - LLL is vendor ISR, ULL is Mayfly ISR concept, Host is kernel thread.
149 ----------
170 * Mayfly are multi-instance scalable ISR execution contexts
173 * Execution priorities map to IRQ priorities
175 * Race-to-idle execution
176 * Lock-less, bare metal
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/Zephyr-Core-3.5.0/lib/acpi/
Dacpi.c4 * SPDX-License-Identifier: Apache-2.0
45 ret = -EIO; in check_init_status()
184 LOG_ERR("No ACPI node with given name: %s", bus_name); in acpi_evaluate_method()
188 if (handle->Type != ACPI_TYPE_DEVICE) { in acpi_evaluate_method()
189 LOG_ERR("No ACPI node foud with given name: %s", bus_name); in acpi_evaluate_method()
198 LOG_ERR("No entry for the ACPI node with given name: %s", bus_name); in acpi_evaluate_method()
238 return -ENODEV; in acpi_get_irq_table()
246 LOG_ERR("unable to retrieve IRQ Routing Table: %s", bus_name); in acpi_get_irq_table()
247 return -EIO; in acpi_get_irq_table()
251 if (!bus->pci_prt_table[i].SourceIndex) { in acpi_get_irq_table()
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_intel.c2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
29 #include <zephyr/irq.h>
93 ((const struct gpio_intel_config *)(_dev)->config)
94 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
140 struct gpio_intel_data *data = dev->data; in check_perm()
141 const struct gpio_intel_config *cfg = dev->config; in check_perm()
144 pin_offset = cfg->pin_offset; in check_perm()
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/Zephyr-Core-3.5.0/drivers/bluetooth/hci/
Dspi.c1 /* spi.c - SPI based Bluetooth driver */
8 * SPDX-License-Identifier: Apache-2.0
53 * required by the SPI slave, as the legacy spi_transceive requires both RX/TX
57 #define SPI_MAX_MSG_LEN 255 /* As defined by X-NUCLEO-IDB04A1 BSP */
65 #define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
112 /* Define a limit when reading IRQ high */
133 /* In case of BlueNRG-MS, it is necessary to prevent SPI driver to release CS,
209 * (See section 5.2 of BlueNRG-MS datasheet)
234 LOG_DBG("IRQ Pin: %d", pin_state); in irq_pin_high()
246 /* Limit attempts on BlueNRG-MS as we might */ in exit_irq_high_loop()
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/Zephyr-Core-3.5.0/include/zephyr/arch/arc/
Darch.h4 * SPDX-License-Identifier: Apache-2.0
12 * included by the kernel interface architecture-abstraction header
24 #include "sys-io-common.h"
27 #include <zephyr/arch/arc/v2/irq.h>
65 * - otherwise all interrupts will use same register bank. Such configuration isn't supported in
86 #error "Non-multithreading mode isn't supported on SMP targets"
110 * For regions that are NOT the minimum size, this define has no semantics
132 /* Kernel-only stacks have the following layout if a stack guard is enabled:
134 * +------------+ <- thread.stack_obj
136 * +------------+ <- thread.stack_info.start
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Duart.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
68 * RS-485 half-duplex. This error is only valid on UARTs that
78 UART_CFG_PARITY_NONE, /**< No parity */
110 UART_CFG_FLOW_CTRL_NONE, /**< No flow control */
128 * @defgroup uart_interrupt Interrupt-driven UART API
143 * @brief For configuring IRQ on each individual UART device.
165 * - Provide second buffer using uart_rx_buf_rsp, when first buffer is
167 * - Ignore the event, this way when current buffer is filled
172 * is counted from last byte received i.e. if no data was received, there
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/Zephyr-Core-3.5.0/arch/xtensa/core/
Dxtensa-asm2.c4 * SPDX-License-Identifier: Apache-2.0
7 #include <xtensa-asm2.h>
30 /* Not-a-cpu ID Ensures that the first time this is run, the in xtensa_init_stack()
36 thread->arch.last_cpu = -1; in xtensa_init_stack()
39 * A0-A3 spill area for the caller of the entry function, in xtensa_init_stack()
45 const int bsasz = sizeof(*frame) - 16; in xtensa_init_stack()
47 frame = (void *)(((char *) stack_top) - bsasz); in xtensa_init_stack()
51 frame->bsa.pc = (uintptr_t)z_thread_entry; in xtensa_init_stack()
52 frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1); in xtensa_init_stack()
55 frame->bsa.threadptr = thread->tls; in xtensa_init_stack()
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