Lines Matching +full:no +full:- +full:legacy +full:- +full:irq

2  * Copyright (c) 2018-2021 Intel Corporation
4  * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/irq.h>
15 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
25  * specific. The timers are implemented as a single up-counter with
39  * COUNTER_CLK_PERIOD is not in femtoseconds (1e-15 sec).
44 #define GCONF_LR			BIT(1) /* legacy interrupt routing, */
116  * 32-bit of the General Capabilities and ID Register. This can
209 /* COUNTER_CLK_PERIOD (CLK_PERIOD_REG) is in femtoseconds (1e-15 sec) */
216  * has no "sense" cell.
220 __WARN("HPET_INT_LEVEL_TRIGGER has no effect, DTS setting is used instead")
263 	if (unlikely((int64_t)(next - now) <= 0)) {  in hpet_timer_comparator_set_safe()
271 		} while ((int64_t)(next - now) <= 0);  in hpet_timer_comparator_set_safe()
300 		int64_t diff = (int64_t)(now - last_count);  in hpet_isr()
306 	uint32_t dticks = (uint32_t)((now - last_count) / cyc_per_tick);  in hpet_isr()
323 static void config_timer0(unsigned int irq)  in config_timer0()  argument
327 	/* 5-bit IRQ field starting at bit 9 */  in config_timer0()
328 	val = (val & ~(0x1f << 9)) | ((irq & 0x1f) << 9);  in config_timer0()
345 	/* Noop, the HPET is a single system-wide device and it's  in smp_timer_init()
386 	uint32_t ret = (uint32_t)((now - last_count) / cyc_per_tick);  in sys_clock_elapsed()
448 	/* Note: we set the legacy routing bit, because otherwise  in sys_clock_driver_init()
450 	 * interrupts into the same IRQ.  But that means we're then  in sys_clock_driver_init()
451 	 * forced to use IRQ2 contra the way the kconfig IRQ selection  in sys_clock_driver_init()