/Zephyr-latest/dts/bindings/ethernet/ |
D | davicom,dm8806-phy.yaml | 2 # SPDX-License-Identifier: Apache-2.0 4 description: Davicom DM8806 Ethernet MAC and PHY with RMII interface 6 compatible: "davicom,dm8806-phy" 8 include: [ethernet-phy.yaml] 10 on-bus: mdio 16 5-bit PHY address for Internal PHY Registers group of Davicom DM8806 MAC 17 PHY Ethernet Switch Controller, separate for each MAC PHY, build in DM8806 18 and correlate with Ethenet port. DM8806 has five MAC PHY inside, but it is 20 communicate with all of them. Each MAC PHY has its own PHY address, which 21 together with Register address creates the absolute address of the [all …]
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D | silabs,gecko-ethernet.yaml | 3 # SPDX-License-Identifier: Apache-2.0 7 compatible: "silabs,gecko-ethernet" 9 include: ethernet-controller.yaml 20 # PHY address 21 phy-address: 24 description: address of the PHY on the MDIO bus 27 location-rmii: 32 # PHY management interface location 33 location-mdio: 36 description: location of MDC and MDIO pins, configuration defined as <location> [all …]
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D | adi,adin2111.yaml | 2 # SPDX-License-Identifier: Apache-2.0 5 ADIN2111 standalone 10BASE-T1L Ethernet controller with SPI interface. 12 spi-max-frequency = <25000000>; 13 int-gpios = <&gpioe 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 14 reset-gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; 16 local-mac-address = [ CA 2F B7 10 23 63 ]; 19 local-mac-address = [ 3C 82 D4 A2 29 8E ]; 21 mdio: mdio { 22 compatible = "adi,adin2111-mdio"; 24 #address-cells = <1>; [all …]
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D | adi,adin1110.yaml | 2 # SPDX-License-Identifier: Apache-2.0 5 ADIN1110 standalone 10BASE-T1L Ethernet controller with SPI interface. 12 spi-max-frequency = <25000000>; 13 int-gpios = <&gpioe 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 14 reset-gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; 16 local-mac-address = [ CA 2F B7 10 23 63 ]; 18 mdio: mdio { 19 compatible = "adi,adin2111-mdio"; 21 #address-cells = <1>; 22 #size-cells = <0>; [all …]
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D | xlnx,gem.yaml | 3 # SPDX-License-Identifier: Apache-2.0 10 include: ethernet-controller.yaml 19 clock-frequency: 26 is determined by the current link speed reported by the PHY, to 27 which it will be adjusted at run-time. Therefore, the value of this 29 respective GEM's TX clock - by default, this is the IO PLL. 31 mdc-divider: 36 applied to the LPD_LSBUS clock in order to derive MDIO interface 37 clock driving communications with the attached PHY. Refer to the 42 init-mdio-phy: [all …]
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D | adi,adin2111-phy.yaml | 2 # SPDX-License-Identifier: Apache-2.0 4 description: ADIN2111 PHY 6 compatible: "adi,adin2111-phy" 8 include: phy.yaml 10 on-bus: mdio 15 description: 5-bit physical/port address (PRTAD). 16 led0-en: 19 led1-en: 22 disable-tx-mode-24v:
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/Zephyr-latest/tests/drivers/build_all/ethernet/ |
D | app.overlay | 3 * SPDX-License-Identifier: Apache-2.0 8 #address-cells = <1>; 9 #size-cells = <1>; 13 gpio-controller; 15 #gpio-cells = <0x2>; 22 test_mdio: mdio { 23 compatible = "zephyr,mdio-gpio"; 24 mdc-gpios = <&test_gpio 0 0>; 25 mdio-gpios = <&test_gpio 0 0>; 27 #address-cells = <1>; [all …]
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D | spi_devices.overlay | 4 * SPDX-License-Identifier: Apache-2.0 9 * with real-world devicetree nodes, to allow these tests to run on 15 #address-cells = <1>; 16 #size-cells = <1>; 20 gpio-controller; 22 #gpio-cells = <0x2>; 27 #address-cells = <1>; 28 #size-cells = <0>; 32 clock-frequency = <2000000>; 35 cs-gpios = <&test_gpio 0 0>, [all …]
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/Zephyr-latest/dts/arm64/fvp/ |
D | fvp-aemv8r.dtsi | 3 * SPDX-License-Identifier: Apache-2.0 7 #include <arm64/armv8-r.dtsi> 8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 12 #address-cells = <1>; 13 #size-cells = <0>; 17 compatible = "arm,cortex-r82"; 23 compatible = "arm,cortex-r82"; 29 compatible = "arm,cortex-r82"; 35 compatible = "arm,cortex-r82"; 41 compatible = "arm,armv8-timer"; [all …]
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/Zephyr-latest/drivers/mdio/ |
D | mdio_nxp_enet.c | 2 * Copyright 2023-2024 NXP 4 * SPDX-License-Identifier: Apache-2.0 11 #include <zephyr/net/mdio.h> 12 #include <zephyr/drivers/mdio.h> 36 * in order to wait for the completion of an MDIO transaction. 37 * It returns -ETIMEDOUT if timeout occurs as specified in DT, 39 * operation, otherwise -EIO. 43 struct nxp_enet_mdio_data *data = dev->data; in nxp_enet_mdio_wait_xfer() 47 return -EWOULDBLOCK; in nxp_enet_mdio_wait_xfer() 50 if (!data->interrupt_up) { in nxp_enet_mdio_wait_xfer() [all …]
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D | mdio_nxp_enet_qos.c | 4 * SPDX-License-Identifier: Apache-2.0 9 #include <zephyr/net/mdio.h> 10 #include <zephyr/drivers/mdio.h> 41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy() 47 static int do_transaction(struct mdio_transaction *mdio) in do_transaction() argument 49 enet_qos_t *base = mdio->base; in do_transaction() 53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction() 55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction() 56 base->MAC_MDIO_DATA = in do_transaction() 58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction() [all …]
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D | mdio_gpio.c | 4 * SPDX-License-Identifier: Apache-2.0 13 #include <zephyr/drivers/mdio.h> 34 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 1); in mdio_gpio_clock_the_bit() 36 gpio_pin_set_dt(&dev_cfg->mdc_gpio, 0); in mdio_gpio_clock_the_bit() 41 gpio_pin_configure_dt(&dev_cfg->mdio_gpio, dir ? GPIO_OUTPUT_ACTIVE : GPIO_INPUT); in mdio_gpio_dir() 54 if (gpio_pin_get_dt(&dev_cfg->mdio_gpio) == 1) { in mdio_gpio_read() 68 v_data <<= 32 - v_len; in mdio_gpio_write() 69 for (; v_len > 0; v_len--) { in mdio_gpio_write() 70 gpio_pin_set_dt(&dev_cfg->mdio_gpio, (v_data & MDIO_GPIO_MSB) ? 1 : 0); in mdio_gpio_write() 79 const struct mdio_gpio_config *const dev_cfg = dev->config; in mdio_gpio_transfer() [all …]
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/Zephyr-latest/drivers/ethernet/ |
D | phy_xlnx_gem.c | 4 * PHY management interface implementation 6 * - Marvell Alaska 88E1111 (QEMU simulated PHY) 7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard) 8 * - Texas Instruments TLK105 9 * - Texas Instruments DP83822 12 * SPDX-License-Identifier: Apache-2.0 25 /* Basic MDIO read / write functions for PHY access */ 28 * @brief Read PHY data via the MDIO interface 29 * Reads data from a PHY attached to the respective GEM's MDIO interface 31 * @param base_addr Base address of the GEM's register space [all …]
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D | phy_gecko.c | 5 * SPDX-License-Identifier: Apache-2.0 8 /* SiLabs Giant Gecko GG11 Ethernet PHY driver. */ 18 /* Maximum time to establish a link through auto-negotiation for 19 * 10BASE-T, 100BASE-TX is 3.7s, to add an extra margin the timeout 24 /* Enable MDIO serial bus between MAC and PHY. */ 27 eth->NETWORKCTRL |= ETH_NETWORKCTRL_MANPORTEN; in mdio_bus_enable() 30 /* Enable MDIO serial bus between MAC and PHY. */ 33 eth->NETWORKCTRL &= ~ETH_NETWORKCTRL_MANPORTEN; in mdio_bus_disable() 36 /* Wait PHY operation complete. */ 41 while (!(eth->NETWORKSTATUS & ETH_NETWORKSTATUS_MANDONE)) { in mdio_bus_wait() [all …]
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D | eth_gecko.c | 5 * SPDX-License-Identifier: Apache-2.0 12 * - no link monitoring through PHY interrupt 54 eth->NETWORKCTRL &= ~(ETH_NETWORKCTRL_ENBTX | ETH_NETWORKCTRL_ENBRX); in link_configure() 57 val = eth->NETWORKCFG; in link_configure() 61 eth->NETWORKCFG = val; in link_configure() 64 eth->NETWORKCTRL |= (ETH_NETWORKCTRL_ENBTX | ETH_NETWORKCTRL_ENBRX); in link_configure() 69 const struct eth_gecko_dev_cfg *const cfg = dev->config; in eth_gecko_setup_mac() 70 ETH_TypeDef *eth = cfg->regs; in eth_gecko_setup_mac() 74 /* PHY auto-negotiate link parameters */ in eth_gecko_setup_mac() 75 result = phy_gecko_auto_negotiate(&cfg->phy, &link_status); in eth_gecko_setup_mac() [all …]
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/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/ |
D | fvp_base_revc_2xaemv8a.dts | 3 * SPDX-License-Identifier: Apache-2.0 6 /dts-v1/; 9 #include <arm64/armv8-a.dtsi> 10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 23 zephyr,shell-uart = &uart0; 27 compatible = "arm,psci-0.2"; 32 #address-cells = <1>; 33 #size-cells = <0>; 37 compatible = "arm,cortex-a53"; 43 compatible = "arm,cortex-a53"; [all …]
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/Zephyr-latest/dts/arm/xilinx/ |
D | zynqmp.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 8 #include <arm/armv7-r.dtsi> 9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h> 16 compatible = "xlnx,pinctrl-zynqmp"; 19 compatible = "soc-nv-flash"; 24 compatible = "mmio-sram"; 29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 31 zephyr,memory-region = "OCM"; 40 interrupt-names = "irq_0"; [all …]
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D | zynq7000.dtsi | 3 * SPDX-License-Identifier: Apache-2.0 7 #include <arm/armv7-a.dtsi> 8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h> 13 interrupt-parent = <&gic>; 16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 18 zephyr,memory-region = "OCM_LOW"; 22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 24 zephyr,memory-region = "OCM_HIGH"; 28 compatible = "arm,armv8-timer"; [all …]
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/Zephyr-latest/boards/espressif/esp32_ethernet_kit/ |
D | esp32_ethernet_kit_procpu.dts | 4 * SPDX-License-Identifier: Apache-2.0 6 /dts-v1/; 9 #include "esp32_ethernet_kit-pinctrl.dtsi" 13 model = "Espressif ESP32-Ethernet-Kit PROCPU"; 17 uart-0 = &uart0; 24 zephyr,shell-uart = &uart0; 26 zephyr,code-partition = &slot0_partition; 27 zephyr,bt-hci = &esp32_bt_hci; 33 current-speed = <115200>; 34 pinctrl-0 = <&uart0_default>; [all …]
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/Zephyr-latest/drivers/ethernet/phy/ |
D | phy_mii.c | 2 * Copyright (c) 2021 IP-Logix Inc. 5 * SPDX-License-Identifier: Apache-2.0 14 #include <zephyr/drivers/mdio.h> 15 #include <zephyr/net/phy.h> 26 const struct device * const mdio; member 39 /* Offset to align capabilities bits of 1000BASE-T Control and Status regs */ 50 const struct phy_mii_dev_config *const cfg = dev->config; in phy_mii_reg_read() 52 /* if there is no mdio (fixed-link) it is not supported to read */ in phy_mii_reg_read() 53 if (cfg->mdio == NULL) { in phy_mii_reg_read() 54 return -ENOTSUP; in phy_mii_reg_read() [all …]
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/Zephyr-latest/boards/st/nucleo_h563zi/ |
D | nucleo_h563zi.dts | 5 * SPDX-License-Identifier: Apache-2.0 8 /dts-v1/; 9 #include "nucleo_h563zi-common.dtsi" 13 model = "STMicroelectronics STM32H563ZI-NUCLEO board"; 14 compatible = "st,stm32h563zi-nucleo"; 16 #address-cells = <1>; 17 #size-cells = <1>; 21 zephyr,shell-uart = &usart3; 24 zephyr,code-partition = &slot0_partition; 32 pwm-led0 = &pwm_led_1; [all …]
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/Zephyr-latest/boards/adi/eval_adin2111ebz/ |
D | adi_eval_adin2111ebz.dts | 4 * SPDX-License-Identifier: Apache-2.0 7 /dts-v1/; 10 #include <st/l4/stm32l4s5qiix-pinctrl.dtsi> 13 model = "Analog Devices Inc. EVAL-ADIN2111EBZ board"; 14 compatible = "adi,eval-adin2111ebz"; 18 zephyr,shell-uart = &usart1; 21 zephyr,code-partition = &slot0_partition; 25 compatible = "gpio-leds"; 67 div-m = <4>; 68 mul-n = <40>; [all …]
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/Zephyr-latest/boards/atmel/sam0/same54_xpro/ |
D | same54_xpro.dts | 4 * SPDX-License-Identifier: Apache-2.0 7 /dts-v1/; 9 #include "same54_xpro-pinctrl.dtsi" 10 #include <zephyr/dt-bindings/input/input-event-codes.h> 18 zephyr,shell-uart = &sercom2; 26 pwm-led0 = &pwm_led0; 28 i2c-0 = &sercom7; 32 compatible = "gpio-leds"; 40 compatible = "pwm-leds"; 47 compatible = "gpio-keys"; [all …]
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/Zephyr-latest/boards/renesas/mck_ra8t1/ |
D | mck_ra8t1.dts | 3 * SPDX-License-Identifier: Apache-2.0 6 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <zephyr/dt-bindings/adc/adc.h> 11 #include "mck_ra8t1-pinctrl.dtsi" 14 model = "Renesas MCK-RA8T1"; 21 zephyr,shell-uart = &uart3; 23 zephyr,flash-controller = &flash1; 28 compatible = "gpio-leds"; 54 clock-frequency = <DT_FREQ_M(24)>; [all …]
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/Zephyr-latest/samples/boards/nxp/s32/netc/ |
D | README.rst | 1 .. zephyr:code-sample:: nxp_s32_netc 10 for the different use-cases: 13 Ethernet PHY through EMDIO. 15 2. Zephyr application controls the PSI, Virtual SI 1, and the Ethernet PHY 18 The sample enables the net-shell and mdio-shell (only available when Zephyr 28 To run this sample is needed to set-up a host machine running GNU/Linux or Windows 35 To build and run the sample application for use-case 1: 37 .. zephyr-app-commands:: 38 :zephyr-app: samples/boards/nxp/s32/netc 44 .. code-block:: console [all …]
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