Searched full:masking (Results 1 – 25 of 35) sorted by relevance
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_dw_ace.c | 37 * implement a simplified masking architecture. Xtensa INTENABLE
38 * always has the line active, and we do all masking of external
41 * Finally: note that there is an extra layer of masking on ACE. The
47 * Thus, the masking architecture picked here is:
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| D | intc_esp32c3.c | 162 /* set global esp32c3's INTC masking level */ in esp_intr_initialize()
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| /Zephyr-latest/soc/intel/intel_socfpga/common/ |
| D | socfpga_system_manager.h | 35 /* Field Masking */
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| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | cavs-idc.h | 60 * TFC (clear high "DONE" bit). This masking is in ADDITION to the
89 * level 2-5 interrupts). The "mask" field shows the current masking
105 * layer of interrupt masking.
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| /Zephyr-latest/dts/bindings/espi/ |
| D | microchip,xec-espi-host-dev.yaml | 49 and the fixed memory address masking.
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| /Zephyr-latest/dts/bindings/input/ |
| D | kbd-matrix-common.yaml | 63 detection on non existing keys. No masking by default, any combination is
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| /Zephyr-latest/doc/kernel/services/smp/ |
| D | smp.rst | 38 critical sections using interrupt masking. These APIs continue to
39 work via an emulation layer (see below), but the masking technique
92 instruction) interrupt masking operation. That, and the fact that the
234 scheduling the highest N priority ready threads to execute. When CPU masking
240 When CPU masking is not in play, the optimal set of threads is the same
241 as the valid set of threads. However when CPU masking is in play, there
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| /Zephyr-latest/include/zephyr/sys/ |
| D | sys_io.h | 250 * @brief Masking the designated bits from addr to 1
252 * This functions masking designated bits from addr to 1.
260 * @brief Masking the designated bits from addr to 0
262 * This functions masking designated bits from addr to 0.
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| /Zephyr-latest/tests/kernel/spinlock/src/ |
| D | main.c | 147 * @brief Test basic mutual exclusion using interrupt masking
152 * interrupt masking.
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/ |
| D | radio_df.c | 321 * adding conditions on the value and masking of the field before in radio_df_cte_tx_aod_2us_set()
334 * adding conditions on the value and masking of the field before in radio_df_cte_tx_aod_4us_set()
347 * of adding conditions on the value and masking of the field before in radio_df_cte_tx_aoa_set()
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_interrupt.h | 43 * provides per-core masking and status checking: ACE_DINT is an array
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_interrupt.h | 41 * provides per-core masking and status checking: ACE_DINT is an array
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/ |
| D | adsp_interrupt.h | 41 * provides per-core masking and status checking: ACE_DINT is an array
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | power.c | 123 * arch_irq_lock() which sets BASEPRI to a non-zero value masking all interrupts
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| D | device_power.c | 59 * ISR after wake. We are masking ISR's from running until we restore
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| /Zephyr-latest/subsys/net/lib/websocket/ |
| D | websocket_internal.h | 96 /** Websocket connection masking value */
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| D | websocket.c | 696 /* Masking */ in websocket_send_msg()
719 /* Add masking value if needed */ in websocket_send_msg()
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| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | controller.rst | 76 This method is called masking.
114 * Filters with Masking
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | power.c | 163 * arch_irq_lock() which sets BASEPRI to a non-zero value masking interrupts at
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| /Zephyr-latest/drivers/timer/ |
| D | intel_adsp_timer.c | 197 /* These platforms have an extra layer of interrupt masking in irq_init()
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| /Zephyr-latest/tests/lib/lockfree/src/ |
| D | test_spsc.c | 68 * @brief Produce and Consume 3 items at a time in a spsc of size 4 to validate masking
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| /Zephyr-latest/arch/arm64/core/ |
| D | thread.c | 116 * - SPSR_ELn: to enable IRQs (we are masking FIQs). in arch_new_thread()
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| /Zephyr-latest/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc.c | 457 /* configure interrupts for MSI-X Per-Vector Masking feature */ in iproc_pcie_ep_init()
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| /Zephyr-latest/tests/net/socket/websocket/src/ |
| D | main.c | 72 * payload length is 12, masking key is e17e8eb9,
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| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_ace20_lnl.dtsi | 449 * masking layer makes it easier for LNL to handle
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