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/Zephyr-latest/dts/bindings/clock/
Dst,stm32-lse-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 LSE Clock
6 compatible: "st,stm32-lse-clock"
8 include: [fixed-clock.yaml]
11 driving-capability:
15 LSE driving capability, within the range 0 to 3.
19 - 0
20 - 1
21 - 2
22 - 3
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/Zephyr-latest/boards/arduino/opta/
Darduino_opta_stm32h747xx_m7.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/h7/stm32h747xihx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "arduino_opta-common.dtsi"
16 compatible = "arduino,opta-m7";
21 zephyr,code-partition = &slot0_partition;
26 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
27 pinctrl-names = "default";
34 clock-frequency = <DT_FREQ_M(25)>;
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/Zephyr-latest/boards/arduino/nicla_vision/
Darduino_nicla_vision_stm32h747xx_m7.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h747a(g-i)ix-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 compatible = "arduino,nicla-vision";
19 zephyr,shell-uart = &lpuart1;
20 zephyr,uart-mcumgr = &lpuart1;
21 zephyr,bt-hci = &bt_hci_uart;
24 zephyr,code-partition = &slot0_partition;
34 compatible = "usb-ulpi-phy";
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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c7 * SPDX-License-Identifier: Apache-2.0
144 return -ENOTSUP; in enabled_clock()
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
157 return -ENOTSUP; in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
163 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
176 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
178 return -ENOTSUP; in stm32_clock_control_off()
181 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
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Dclock_stm32_ll_u5.c6 * SPDX-License-Identifier: Apache-2.0
150 return -ENOTSUP; in enabled_clock()
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
163 return -ENOTSUP; in stm32_clock_control_on()
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
167 pclken->enr); in stm32_clock_control_on()
169 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
182 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
184 return -ENOTSUP; in stm32_clock_control_off()
187 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
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Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
136 r = -ENOTSUP; in enabled_clock()
150 r = -ENOTSUP; in enabled_clock()
157 r = -ENOTSUP; in enabled_clock()
164 r = -ENOTSUP; in enabled_clock()
171 r = -ENOTSUP; in enabled_clock()
178 r = -ENOTSUP; in enabled_clock()
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Dclock_stm32_ll_wb0.c4 * SPDX-License-Identifier: Apache-2.0
43 # error slow-clock source is not enabled
53 # error Invalid device selected as slow-clock
66 "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
108 * NOTE: (size - 1) is required to get the correct count, in measure_lsi_frequency()
113 (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1)); in measure_lsi_frequency()
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
155 * = ------------------------------------------------ in measure_lsi_frequency()
163 * = ------------------------------------------------ in measure_lsi_frequency()
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Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
339 return -ERANGE;
381 return -ENOTSUP;
392 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
394 return -ENOTSUP;
399 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
403 temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus);
418 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
420 return -ENOTSUP;
425 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
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/Zephyr-latest/boards/weact/stm32g431_core/doc/
Dindex.rst3 The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development
7 Modifications USB-C Power Delivery
10 The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1
11 and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and
15 The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to
16 the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx
20 considered reserved for USB-C and not available for other applications.
24 PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or
34 +------------+------------+-------------------------------------+
37 | NVIC | on-chip | nested vector interrupt controller |
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-1.14.rst17 * CVE-2020-10066
18 * CVE-2020-10069
19 * CVE-2020-13601
20 * CVE-2020-13602
32 * :github:`issuenumber` - issue title
34 * :github:`18334` - DNS resolution is broken for some addresses in master/2.0-pre
35 * :github:`19917` - Bluetooth: Controller: Missing LL_ENC_RSP after HCI LTK Negative Reply
36 * :github:`21107` - LL_ASSERT and 'Imprecise data bus error' in LL Controller
37 * :github:`21257` - tests/net/net_pkt failed on mimxrt1050_evk board.
38 * :github:`21299` - bluetooth: Controller does not release buffer on central side after peripheral …
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