6  * SPDX-License-Identifier: Apache-2.0
150 	return -ENOTSUP;  in enabled_clock()
161 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_on()
163 		return -ENOTSUP;  in stm32_clock_control_on()
166 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_on()
167 		     pclken->enr);  in stm32_clock_control_on()
169 	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);  in stm32_clock_control_on()
182 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {  in stm32_clock_control_off()
184 		return -ENOTSUP;  in stm32_clock_control_off()
187 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,  in stm32_clock_control_off()
188 		       pclken->enr);  in stm32_clock_control_off()
203 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
209 	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
210 		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
211 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),  in stm32_clock_control_configure()
212 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));  in stm32_clock_control_configure()
236 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
357 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
360 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
361 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
374 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {  in stm32_clock_control_get_status()
376 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)  in stm32_clock_control_get_status()
377 		    == pclken->enr) {  in stm32_clock_control_get_status()
384 		if (enabled_clock(pclken->bus) == 0) {  in stm32_clock_control_get_status()
412 		return -ERANGE;  in get_vco_input_range()
542 		return -ENOTSUP;  in set_up_plls()
604 		return -ENOTSUP;  in set_up_plls()
626 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);  in set_up_plls()
631 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);  in set_up_plls()
636 		SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);  in set_up_plls()
656 		return -ENOTSUP;  in set_up_plls()
678 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);  in set_up_plls()
683 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);  in set_up_plls()
688 		SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);  in set_up_plls()
706 		/* Check if need to enable HSE bypass feature or not */  in set_up_fixed_clock_sources()
747 			/* Configure LSE bypass */  in set_up_fixed_clock_sources()
751 		/* Enable LSE Oscillator */  in set_up_fixed_clock_sources()
753 		/* Wait for LSE ready */  in set_up_fixed_clock_sources()
774 				"MSIS Hardware auto calibration needs LSE clock activation");  in set_up_fixed_clock_sources()
796 				"MSIK Hardware auto calibration needs LSE clock activation");  in set_up_fixed_clock_sources()
899 		return -ENOTSUP;  in stm32_clock_control_init()