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/Zephyr-latest/soc/nxp/lpc/lpc55xxx/
DKconfig96 In the LPC55XXX Family, this is currently being used to set the
102 bool "LPC55xxx's second core"
DKconfig.soc9 default "lpc55xxx" if SOC_SERIES_LPC55XXX
/Zephyr-latest/dts/bindings/flash_controller/
Dnxp,iap-fmc55.yaml6 the lpc55xxx family, except lpc553x
/Zephyr-latest/boards/nxp/lpcxpresso55s06/
Dlpcxpresso55s06.dts14 compatible = "nxp,lpc55xxx", "nxp,lpc";
/Zephyr-latest/soc/nxp/lpc/
Dsoc.yml18 - name: lpc55xxx
/Zephyr-latest/boards/nxp/lpcxpresso55s16/
Dlpcxpresso55s16.dts15 compatible = "nxp,lpc55xxx", "nxp,lpc";
/Zephyr-latest/boards/nxp/lpcxpresso55s69/
Dlpcxpresso55s69_lpc55s69_cpu1.dts14 compatible = "nxp,lpc55xxx", "nxp,lpc";
Dlpcxpresso55s69_lpc55s69_cpu0_ns.dts15 compatible = "nxp,lpc55xxx", "nxp,lpc";
Dlpcxpresso55s69_lpc55s69_cpu0.dts16 compatible = "nxp,lpc55xxx", "nxp,lpc";
/Zephyr-latest/boards/nxp/lpcxpresso55s28/
Dlpcxpresso55s28.dts16 compatible = "nxp,lpc55xxx", "nxp,lpc";
/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wwdt.c68 * LPC55xxx WWDT has a fixed divide-by-4 clock prescaler.
/Zephyr-latest/boards/nxp/lpcxpresso55s36/
Dlpcxpresso55s36.dts15 compatible = "nxp,lpc55xxx", "nxp,lpc";
/Zephyr-latest/modules/
DKconfig.mcux114 the LPC55xxx family SoCs.
/Zephyr-latest/doc/releases/
Dmigration-guide-3.5.rst220 * The LPC55XXX series SOC (except LPC55S06) default main clock has been
Drelease-notes-3.6.rst161 * LPC55xxx: Fixed the system hardware clock cycle rate.
359 * Added support for the MRT counter for NXP RT6xx, RT5xx and LPC55xxx.
Drelease-notes-2.2.rst420 * extend MCUX flash drive to support LPC55xxx devices