1/* 2 * Copyright 2019,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8 9#include <nxp/nxp_lpc55S6x.dtsi> 10#include "lpcxpresso55s69.dtsi" 11#include <zephyr/dt-bindings/pwm/pwm.h> 12#include <zephyr/dt-bindings/input/input-event-codes.h> 13 14/ { 15 model = "NXP LPCXpresso55S69 board"; 16 compatible = "nxp,lpc55xxx", "nxp,lpc"; 17 18 cpus { 19 /delete-node/ cpu@1; 20 }; 21 22 aliases{ 23 sw0 = &user_button_1; 24 sw1 = &user_button_2; 25 sw2 = &user_button_3; 26 watchdog0 = &wwdt0; 27 /* For pwm test suites */ 28 pwm-0 = &sc_timer; 29 pwm-led0 = &red_pwm_led; 30 red-pwm-led = &red_pwm_led; 31 sdhc0 = &sdhc0; 32 accel0 = &mma8652fc; 33 sdhc0 = &sdif; 34 mcuboot-button0 = &user_button_1; 35 }; 36 37 chosen { 38 zephyr,sram = &sram0; 39 zephyr,flash = &flash0; 40 zephyr,code-partition = &slot0_partition; 41 zephyr,uart-mcumgr = &flexcomm0; 42 zephyr,code-cpu1-partition = &slot0_ns_partition; 43 zephyr,sram-cpu1-partition = &sram3; 44 zephyr,console = &flexcomm0; 45 zephyr,shell-uart = &flexcomm0; 46 zephyr,entropy = &rng; 47 }; 48 49 gpio_keys { 50 compatible = "gpio-keys"; 51 user_button_1: button_0 { 52 label = "User SW1"; 53 gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; 54 zephyr,code = <INPUT_KEY_0>; 55 }; 56 user_button_2: button_1 { 57 label = "User SW2"; 58 gpios = <&gpio1 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 59 zephyr,code = <INPUT_KEY_1>; 60 }; 61 user_button_3: button_2 { 62 label = "User SW3"; 63 gpios = <&gpio1 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 64 zephyr,code = <INPUT_KEY_2>; 65 }; 66 }; 67 68 pwmleds { 69 compatible = "pwm-leds"; 70 red_pwm_led: red_pwm_led { 71 pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; 72 label = "Red PWM LED"; 73 status = "okay"; 74 }; 75 }; 76}; 77 78/* 79 * Default for this board is to allocate SRAM0-2 to cpu0 but the 80 * application can have an application specific device tree to 81 * allocate the SRAM0-4 differently. 82 * 83 * For example, SRAM0-3 could be allocated to cpu0 with only SRAM4 84 * for cpu1. This would require the zephyr,sram chosen value for cpu1 85 * to be changed to sram4 and the value of sram0 to have a DT_SIZE_K 86 * of 256. 87 * 88 */ 89&sram0 { 90 compatible = "mmio-sram"; 91 reg = <0x20000000 DT_SIZE_K(192)>; 92}; 93 94&gpio0 { 95 status = "okay"; 96}; 97 98&gpio1 { 99 status = "okay"; 100}; 101 102&green_led { 103 status = "okay"; 104}; 105 106&red_led { 107 status = "okay"; 108}; 109 110&flexcomm0 { 111 status = "okay"; 112}; 113 114&flexcomm4 { 115 status = "okay"; 116}; 117 118&sdif { 119 status = "okay"; 120 pinctrl-0 = <&pinmux_sdif_default>; 121 pinctrl-names = "default"; 122 mmc { 123 compatible = "zephyr,sdmmc-disk"; 124 disk-name = "SD"; 125 status = "okay"; 126 }; 127}; 128 129&hs_lspi { 130 status = "okay"; 131 cs-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 132}; 133 134&wwdt0 { 135 status = "okay"; 136}; 137 138&adc0 { 139 status = "okay"; 140 pinctrl-0 = <&pinmux_lpadc0>; 141 pinctrl-names = "default"; 142}; 143 144&mailbox0 { 145 status = "okay"; 146}; 147 148&usbfs { 149 pinctrl-0 = <&pinmux_usbfs>; 150 pinctrl-names = "default"; 151}; 152 153zephyr_udc0: &usbhs { 154 status = "okay"; 155 phy_handle = <&usbphy1>; 156}; 157 158&usbphy1 { 159 status = "okay"; 160 tx-d-cal = <5>; 161 tx-cal-45-dp-ohms = <10>; 162 tx-cal-45-dm-ohms = <10>; 163}; 164 165&ctimer0 { 166 status = "okay"; 167}; 168 169&ctimer1 { 170 status = "okay"; 171}; 172 173&ctimer2 { 174 status = "okay"; 175}; 176 177&ctimer3 { 178 status = "okay"; 179}; 180 181&ctimer4 { 182 status = "okay"; 183}; 184 185/* I2S receive channel */ 186i2s0: &flexcomm6 { 187 status = "okay"; 188 compatible = "nxp,lpc-i2s"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191}; 192 193/* I2S transmit channel */ 194i2s1: &flexcomm7 { 195 status = "okay"; 196 compatible = "nxp,lpc-i2s"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199}; 200 201&sc_timer { 202 status = "okay"; 203}; 204 205&dma0 { 206 status = "okay"; 207}; 208 209&dma1 { 210 status = "okay"; 211}; 212 213&mrt_channel0 { 214 status = "okay"; 215}; 216