Home
last modified time | relevance | path

Searched +full:local +full:- +full:ipi +full:- +full:id (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/dts/bindings/ipm/
Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: Apache-2.0
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
8 compatible: "xlnx,zynqmp-ipi-mailbox"
16 description: IPI control and status register space
18 reg-names:
19 type: string-array
22 local-ipi-id:
24 description: Host Xilinx IPI agent ID of which the mailbox is connected to.
27 child-binding:
[all …]
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp_rpu.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "arm,cortex-r5f";
23 rpu0_ipi: zynqmp-ipi@ff310000 {
25 compatible = "xlnx,zynqmp-ipi-mailbox";
26 #address-cells = <1>;
27 #size-cells = <1>;
30 reg-names = "host_ipi_reg";
33 local-ipi-id = <1>;
[all …]
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dloapic.h1 /* loapic.h - public LOAPIC APIs */
6 * SPDX-License-Identifier: Apache-2.0
16 /* Local APIC Register Offset */
18 #define LOAPIC_ID 0x020 /* Local APIC ID Reg */
19 #define LOAPIC_VER 0x030 /* Local APIC Version Reg */
27 #define LOAPIC_ISR 0x100 /* In-service Reg */
42 #define LOAPIC_SELF_IPI 0x3f0 /* Self IPI Reg, only support in X2APIC mode */
46 #define LOAPIC_ICR_IPI_OTHERS 0x000C4000U /* normal IPI to other CPUs */
70 * @brief Read 64-bit value from the local APIC in x2APIC mode.
81 * @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
[all …]
/Zephyr-latest/doc/kernel/services/smp/
Dsmp.rst26 non-Zephyr code).
54 on top of the pre-existing :c:struct:`atomic_` layer (itself usually
65 re-acquire it or it will deadlock (it is perfectly legal to nest
71 recursive semantics above, spinlocks in single-CPU contexts produce
85 and that it is re-acquired when necessary to restore the lock state
107 :c:func:`k_thread_cpu_mask_disable` with a particular CPU ID will prevent
109 :c:func:`k_thread_cpu_mask_enable` will re-enable execution. There are also
113 suspended, otherwise an ``-EINVAL`` will be returned.
116 involved in doing the per-CPU mask test requires that the list be
117 traversed in full. The kernel does not keep a per-CPU run queue.
[all …]
/Zephyr-latest/arch/riscv/
DKconfig1 # Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
3 # SPDX-License-Identifier: Apache-2.0
13 bool "Hard-float calling convention"
17 This option enables the hard-float calling convention.
24 bool "RISC-V global pointer relative addressing"
31 Note: To support this feature, RISC-V SoC needs to initialize
51 This is for RISC-V implementations that require every mret to be
52 balanced with an ecall. This is not required by the RISC-V spec
57 prompt "RISC-V SMP IPI implementation"
63 bool "CLINT-based IPI"
[all …]
/Zephyr-latest/arch/x86/core/intel64/
Dcpu.c3 * SPDX-License-Identifier: Apache-2.0
22 * Map of CPU logical IDs to CPU local APIC IDs. By default,
46 * Send the INIT/STARTUP IPI sequence required to start up CPU 'cpu_num', which
62 x86_cpu_loapics[cpu_num] = lapic->Id; in arch_cpu_start()
95 /* Per-CPU initialization, C domain. On the first CPU, z_prep_c is the
102 x86_cpu_loapics[cpuboot->cpu_id], "APIC ID miss match!"); in z_x86_cpu_init()
106 if (cpuboot->cpu_id == 0U) { in z_x86_cpu_init()
112 z_loapic_enable(cpuboot->cpu_id); in z_x86_cpu_init()
126 cpuboot->ready++; in z_x86_cpu_init()
127 cpuboot->fn(cpuboot->arg); in z_x86_cpu_init()
Dlocore.S3 * SPDX-License-Identifier: Apache-2.0
22 /* Long mode, no-execute, syscall */
25 /* Paging, write-protect */
75 /* Use 32-bit instructions due to assembler fussiness with large
85 .word __X86_TSS64_SIZEOF-1
92 /* The .locore section begins the page-aligned initialization region
95 * via a startup IPI. It's is ALSO used by some loaders (well,
96 * ACRN...) who hard-coded the address by inspecting _start on a
97 * non-SMP build.
108 * scribble over it with 8 0x90 bytes (which is the 1-byte NOP) and be
[all …]
/Zephyr-latest/kernel/
Dsched.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <ipi.h>
50 * > 0 -> thread 1 priority > thread 2 priority
51 * = 0 -> thread 1 priority == thread 2 priority
52 * < 0 -> thread 1 priority < thread 2 priority
60 int32_t b1 = thread_1->base.prio; in z_sched_prio_cmp()
61 int32_t b2 = thread_2->base.prio; in z_sched_prio_cmp()
64 return b2 - b1; in z_sched_prio_cmp()
71 * guaranteed to be (2's complement) non-negative. We can in z_sched_prio_cmp()
75 uint32_t d1 = thread_1->base.prio_deadline; in z_sched_prio_cmp()
[all …]
/Zephyr-latest/include/zephyr/arch/
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
82 * through the full 64 bit space, wrapping at 2^64-1. Hardware with
92 * @addtogroup arch-threads
126 * buffer, defined as the area usable for thread stack context and thread-
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
[all …]
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
249 newly created informational-only callback struct :c:struct:`bt_conn_auth_info_cb`.
[all …]
Drelease-notes-2.6.rst13 * Added support for 64-bit ARCv3
14 * Split ARM32 and ARM64, ARM64 is now a top-level architecture
15 * Added initial support for Arm v8.1-m and Cortex-M55
22 https://github.com/zephyrproject-rtos/example-application
34 * CVE-2021-3581: Under embargo until 2021-09-04
41 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
46 * Driver APIs now return ``-ENOSYS`` if optional functions are not implemented.
47 If the feature is not supported by the hardware ``-ENOTSUP`` will be returned.
48 Formerly ``-ENOTSUP`` was returned for both failure modes, meaning this change
194 * Added support for null pointer dereferencing detection in Cortex-M.
[all …]
/Zephyr-latest/arch/x86/core/
Dx86_mmu.c2 * Copyright (c) 2011-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017-2020 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
29 * when the mapping was made. This is used to un-apply memory domain memory
51 * - If the entire entry is zero, it's an un-mapped virtual page
52 * - If PTE_ZERO is set, we flipped this page due to KPTI
53 * - Otherwise, this was a page-out
87 /* How many bits to right-shift a virtual address to obtain the
116 * See Figures 4-4, 4-7, 4-11 in the Intel SDM, vol 3A
154 /* 32-bit */
[all …]