Lines Matching +full:local +full:- +full:ipi +full:- +full:id

1 # Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
3 # SPDX-License-Identifier: Apache-2.0
13 	bool "Hard-float calling convention"
17 	  This option enables the hard-float calling convention.
24 	bool "RISC-V global pointer relative addressing"
31 	  Note: To support this feature, RISC-V SoC needs to initialize
51 	  This is for RISC-V implementations that require every mret to be
52 	  balanced with an ecall. This is not required by the RISC-V spec
57 	prompt "RISC-V SMP IPI implementation"
63 	bool "CLINT-based IPI"
66 	  Use CLINT-based IPI implementation.
69 	bool "Custom IPI implementation"
71 	  Allow custom IPI implementation.
74 	   - arch_sched_directed_ipi()
75 	   - arch_flush_fpu_ipi() if CONFIG_FPU_SHARING
76 	   - arch_spin_relax() if CONFIG_FPU_SHARING
77 	   - arch_smp_init()
94 	  Option selected by SoCs implementing the RISC-V privileged ISA.
100 	  Enable low-level SOC-specific hardware stacking / unstacking
112 	  - SOC_ISR_SW_STACKING: macro guarded by _ASMLANGUAGE called by the
117 	  - SOC_ISR_SW_UNSTACKING: macro guarded by _ASMLANGUAGE called by the
121 	  - SOC_ISR_STACKING_ESF_DECLARE: structure declaration for the ESF
139 	  platform-specific versions named z_soc_irq_lock(), z_soc_irq_unlock()
143 	  the RISC-V SoC needs to do something different and more than reading and
150 	  platform-specific versions named z_soc_sys_read*() and z_soc_sys_write*().
153 	  the RISC-V SoC needs to do something different and more than reading and
163 	bool "SOC-based context saving in IRQ handlers"
166 	  Enable low-level SOC-specific context management, for SOCs
174 	  - SOC_ESF_MEMBERS: structure component declarations to
176 	    end in a semicolon, for portability. The generic RISC-V
181 	  - SOC_ESF_INIT: structure contents initializer for struct soc_esf
198 	bool "SOC-based offsets"
203 	  - GEN_SOC_OFFSET_SYMS(): a macro which expands to
219 	  Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
229 	bool "SOC-based interrupt initialization"
231 	  Enable SOC-based interrupt initialization
261 	  intended for inter-hart interrupt signaling and so retained for that
272 	int "Starting HART ID"
275 	  This option sets the starting HART ID for the SMP core.
276 	  For RISC-V systems such as MPFS and FU540 this would be set to 1 to
281 	default -1
283 	  Configures the mask for the HART ID.
284 	  For RISC-V systems with HART ID starting from non-zero value,
294 	  to collect for post-mortem analysis and debug of issues.
297 	bool "RISC-V PMP Support"
329 	  Set this if NA4 (Naturally Aligned 4-byte) mode is not supported.
337 	bool "Enforce power-of-two alignment on PMP memory areas" if !PMP_NO_TOR
403 	  According to the RISC-V Instruction Set Manual: Volume II, Version 20240411
405 	  the floating-point register state imprecisely by reporting the state to be
427 	int "Alignment of RISC-V trap handler in bytes"
431 	  This value configures the alignment of RISC-V trap handling
433 	  the format of MTVEC register which is RISC-V platform-specific.