Lines Matching +full:local +full:- +full:ipi +full:- +full:id

26 non-Zephyr code).
54 on top of the pre-existing :c:struct:`atomic_` layer (itself usually
65 re-acquire it or it will deadlock (it is perfectly legal to nest
71 recursive semantics above, spinlocks in single-CPU contexts produce
85 and that it is re-acquired when necessary to restore the lock state
107 :c:func:`k_thread_cpu_mask_disable` with a particular CPU ID will prevent
109 :c:func:`k_thread_cpu_mask_enable` will re-enable execution.  There are also
113 suspended, otherwise an ``-EINVAL`` will be returned.
116 involved in doing the per-CPU mask test requires that the list be
117 traversed in full.  The kernel does not keep a per-CPU run queue.
138 stack), the address of a local :c:func:`smp_init_top` callback function to
142 The local SMP initialization (:c:func:`smp_init_top`) on each CPU is then
146 many architectures the timer is a per-CPU device and needs to be
157    :figclass: align-center
166 case that state modified on the local CPU needs to be synchronously
175 that system idle be implemented using a low-power mode with as many
179 handle the newly-runnable load.
191 APIs will evolve over time to encompass more functionality (e.g. cross-CPU
192 calls), and that the scheduler-specific calls here will be implemented in
195 Note that not all SMP architectures will have a usable IPI mechanism
203 broadcast an IPI and spin, waiting for the thread to either become
204 "DEAD" or for it to re-enter the queue (in which case we terminate it
207 handling needed in the IPI per se.  This allows us to implement a
208 reasonable fallback when IPI is not available: we can simply spin,
212 Likewise idle wakeups are trivially implementable with an empty IPI
214 have been idle CPUs), we broadcast an IPI.  A foreign CPU will then be
218 Without an IPI, however, a low power idle that requires an interrupt
225 IPI, and this code will only be used for testing purposes or on
228 IPI Cascades
242     may be more than one valid set--one of which may be optimal.
244     To better illustrate the distinction, consider a 2-CPU system with ready
258 There are three types of costs/penalties associated with the IPI cascades--and
260 by the CPU producing the IPI when a new thread preempts the old thread as checks
270 In general, Zephyr kernel code is SMP-agnostic and, like application
275 Per-CPU data
281 running concurrently.  Likewise a kernel-provided interrupt stack
286 within the :c:struct:`_kernel` struct, which has a ``cpus[]`` array indexed by ID.
294 implemented using a CPU-provided register or addressing mode that can
296 make it available to any kernel-mode code.
306 Switch-based context switching
321 with the swap call, and as we don't want per-architecture assembly
323 somewhat lower-level context switch primitives for SMP systems:
333 Similarly, on interrupt exit, switch-based architectures are expected
342 the caller-saved registers on the current thread's stack when interrupted
343 in order to minimize interrupt latency, and preserve the callee-saved