Searched full:lanes (Results 1 – 25 of 25) sorted by relevance
14 data-lanes:18 Number of data lanes.
23 least (pixel clock * bits per output pixel) / number of mipi data lanes
28 data-lanes = <1 2>;43 data-lanes = <1 2>;
44 data-lanes = <1 2>;88 data-lanes = <1 2>;
76 * (pixel clock * bits per pixel) / MIPI data lanes84 data-lanes = <2>;
197 data-lanes = <2>;211 data-lanes = <2>;224 data-lanes = <2>;236 data-lanes = <1>;247 data-lanes = <2>;
52 data-lanes = <1>;
38 data-lanes = <2>;
31 data-lanes = <2>;
129 data-lanes:134 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
10 The micromod standard consists of two lanes with the following
124 /* return bitmask of failed lanes */ in ddr_phy_fixup()
87 /** Number of data lanes. */
151 LOG_ERR("Number of DSI lanes (%d) not supported!", config->data_lanes); in mipi_dsi_stm32_host_init()448 /* Only child data-lanes property at index 0 is taken into account */ \
57 - MIPI® DSI Host controller with two DSI lanes running at up to 500
117 - MIPI® DSI 2 data lanes up to 1 GHz each
120 - MIPI® DSI 2 data lanes up to 1 GHz each
38 - MIPI DSI 1x4 Data Lanes
93 - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each
597 /* Set the number of lanes to DSISETUP0 parameter */ in hx8394_init()
640 /* Power up MIPI PHY HS Tx & LP Rx in 2 data lanes mode */ in ov5640_stream_start()
169 /** Value for mux - DP alternate mode with 4 lanes */
43 - Support for Two Data Lanes
