| /Zephyr-Core-3.6.0/include/zephyr/ |
| D | irq_multilevel.h | 24 * @brief Return IRQ level
27 * @param irq IRQ number in its zephyr format
29 * @return 1 if IRQ level 1, 2 if IRQ level 2, 3 if IRQ level 3
31 static inline unsigned int irq_get_level(unsigned int irq) in irq_get_level() argument
38 if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS) && (irq & mask3) != 0) { in irq_get_level()
42 if (IS_ENABLED(CONFIG_2ND_LEVEL_INTERRUPTS) && (irq & mask2) != 0) { in irq_get_level()
52 * This routine returns the second level irq number of the zephyr irq
55 * @param irq IRQ number in its zephyr format
57 * @return 2nd level IRQ number
59 static inline unsigned int irq_from_level_2(unsigned int irq) in irq_from_level_2() argument
[all …]
|
| D | irq_nextlevel.h | 26 unsigned int irq);
29 unsigned int irq, unsigned int prio,
32 unsigned int irq);
46 * @brief Enable an IRQ in the next level.
51 * @param irq IRQ to be enabled.
54 uint32_t irq) in irq_enable_next_level() argument
59 api->intr_enable(dev, irq); in irq_enable_next_level()
63 * @brief Disable an IRQ in the next level.
68 * @param irq IRQ to be disabled.
71 uint32_t irq) in irq_disable_next_level() argument
[all …]
|
| /Zephyr-Core-3.6.0/soc/riscv/openisa_rv32m1/ |
| D | vector.S | 22 * at byte offset 4 * (IRQ line number).
25 * are handled by the addresses right after the IRQ table.
36 j _isr_wrapper /* IRQ 0 */
37 j _isr_wrapper /* IRQ 1 */
38 j _isr_wrapper /* IRQ 2 */
39 j _isr_wrapper /* IRQ 3 */
40 j _isr_wrapper /* IRQ 4 */
41 j _isr_wrapper /* IRQ 5 */
42 j _isr_wrapper /* IRQ 6 */
43 j _isr_wrapper /* IRQ 7 */
[all …]
|
| D | soc.h | 26 * See gen_isr_tables.py for details on the Zephyr multi-level IRQ
31 * @brief Get an IRQ's level
32 * @param irq The IRQ number in the Zephyr irq.h numbering system
33 * @return IRQ level, either 1 or 2
35 static inline unsigned int rv32m1_irq_level(unsigned int irq) in rv32m1_irq_level() argument
37 return ((irq >> 8) & 0xff) == 0U ? 1 : 2; in rv32m1_irq_level()
41 * @brief Level 1 interrupt line associated with an IRQ
43 * Results are undefined if rv32m1_irq_level(irq) is not 1.
45 * @param The IRQ number in the Zephyr <irq.h> numbering system
46 * @return Level 1 (i.e. event unit) IRQ number associated with irq
[all …]
|
| /Zephyr-Core-3.6.0/drivers/interrupt_controller/ |
| D | intc_vim.c | 11 #include <zephyr/arch/arm/irq.h>
26 /* Reading IRQVEC register, ACTIRQ gets loaded with valid IRQ values */ in z_vim_irq_get_active()
32 /* Check if the irq number is valid, else return invalid irq number. in z_vim_irq_get_active()
52 void z_vim_irq_eoi(unsigned int irq) in z_vim_irq_eoi() argument
64 void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_vim_irq_priority_set() argument
68 if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || in z_vim_irq_priority_set()
70 LOG_ERR("%s: Invalid argument irq = %u prio = %u flags = %u\n", in z_vim_irq_priority_set()
71 __func__, irq, prio, flags); in z_vim_irq_priority_set()
75 sys_write8(prio, VIM_PRI_INT(irq)); in z_vim_irq_priority_set()
77 irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); in z_vim_irq_priority_set()
[all …]
|
| D | intc_system_apic.c | 19 #include <zephyr/irq.h>
22 #define IS_IOAPIC_IRQ(irq) (irq < z_loapic_irq_base()) argument
29 * based on the given IRQ parameter.
42 * @param irq the virtualized IRQ
46 void z_irq_controller_irq_config(unsigned int vector, unsigned int irq, in z_irq_controller_irq_config() argument
49 __ASSERT(irq <= HARDWARE_IRQ_LIMIT, "invalid irq line"); in z_irq_controller_irq_config()
51 if (IS_IOAPIC_IRQ(irq)) { in z_irq_controller_irq_config()
52 z_ioapic_irq_set(irq, vector, flags); in z_irq_controller_irq_config()
54 z_loapic_int_vec_set(irq - z_loapic_irq_base(), vector); in z_irq_controller_irq_config()
59 * @brief Enable an individual interrupt (IRQ)
[all …]
|
| D | intc_swerv_pic.c | 17 #include <zephyr/irq.h>
18 #include <zephyr/arch/riscv/irq.h>
57 void swerv_pic_irq_enable(uint32_t irq) in swerv_pic_irq_enable() argument
61 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_enable()
66 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 1); in swerv_pic_irq_enable()
70 void swerv_pic_irq_disable(uint32_t irq) in swerv_pic_irq_disable() argument
74 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_disable()
79 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 0); in swerv_pic_irq_disable()
83 int swerv_pic_irq_is_enabled(uint32_t irq) in swerv_pic_irq_is_enabled() argument
85 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_is_enabled()
[all …]
|
| D | intc_ioapic.c | 45 * The lower 32 bit value of the redirection table entries for IRQ 0
46 * to 15 are edge triggered positive high, and for IRQ 16 to 23 are level
99 #define BIT_POS_FOR_IRQ_OPTION(irq, option) ((irq) * BITS_PER_IRQ + (option)) argument
101 /* Allocating up to 256 irq bits bufffer for RTEs, RTEs are dynamically found
112 static void ioApicRedSetHi(unsigned int irq, uint32_t upper32);
113 static void ioApicRedSetLo(unsigned int irq, uint32_t lower32);
114 static uint32_t ioApicRedGetLo(unsigned int irq);
115 static void IoApicRedUpdateLo(unsigned int irq, uint32_t value,
144 * interrupt controller driver due to the IRQ virtualization imposed by
192 * @param irq IRQ number to enable
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-int-map.dtsi | 15 irq = <31>;
16 irq-prio = <2>;
20 irq = <15>;
21 irq-prio = <2>;
31 irq = <47>;
32 irq-prio = <2>;
36 irq = <48>;
37 irq-prio = <2>;
41 irq = <49>;
42 irq-prio = <2>;
[all …]
|
| /Zephyr-Core-3.6.0/soc/riscv/common/riscv-privileged/ |
| D | soc_common_irq.c | 12 #include <zephyr/irq.h>
20 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
22 riscv_clic_irq_enable(irq); in arch_irq_enable()
25 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
27 riscv_clic_irq_disable(irq); in arch_irq_disable()
30 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
32 return riscv_clic_irq_is_enabled(irq); in arch_irq_is_enabled()
35 void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_riscv_irq_priority_set() argument
37 riscv_clic_irq_priority_set(irq, prio, flags); in z_riscv_irq_priority_set()
42 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
[all …]
|
| /Zephyr-Core-3.6.0/tests/arch/arm/arm_custom_interrupt/src/ |
| D | arm_custom_interrupt.c | 25 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
26 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
30 int irq = 0; in z_soc_irq_init() local
32 for (; irq < CONFIG_NUM_IRQS; irq++) { in z_soc_irq_init()
33 NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); in z_soc_irq_init()
39 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
41 if (irq == sw_irq_number) { in z_soc_irq_enable()
44 NVIC_EnableIRQ((IRQn_Type)irq); in z_soc_irq_enable()
47 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
49 if (irq == sw_irq_number) { in z_soc_irq_disable()
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-int-map.dtsi | 19 irq = <7>;
20 irq-prio = <2>;
24 irq = <5>;
25 irq-prio = <2>;
29 irq = <11>;
30 irq-prio = <2>;
34 irq = <35>;
35 irq-prio = <2>;
39 irq = <42>;
40 irq-prio = <2>;
[all …]
|
| /Zephyr-Core-3.6.0/subsys/testsuite/include/zephyr/ |
| D | interrupt_util.h | 25 * returning false, here, implies that the IRQ line is in get_available_nvic_line()
55 zassert_true(i >= 0, "No available IRQ line\n"); in get_available_nvic_line()
60 static inline void trigger_irq(int irq) in trigger_irq() argument
62 printk("Triggering irq : %d\n", irq); in trigger_irq()
67 NVIC_SetPendingIRQ(irq); in trigger_irq()
69 NVIC->STIR = irq; in trigger_irq()
77 static inline void trigger_irq(int irq) in trigger_irq() argument
79 printk("Triggering irq : %d\n", irq); in trigger_irq()
81 /* Ensure that the specified IRQ number is a valid SGI interrupt ID */ in trigger_irq()
82 zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq); in trigger_irq()
[all …]
|
| /Zephyr-Core-3.6.0/boards/posix/native_posix/ |
| D | irq_ctrl.c | 6 * HW IRQ controller model
27 * irq handler
41 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
75 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
77 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
80 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
82 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
151 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
153 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
156 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
[all …]
|
| /Zephyr-Core-3.6.0/arch/x86/core/intel64/ |
| D | locore.S | 668 * When we arrive at 'irq' from one of the IRQ(X) stubs,
669 * we're on the "freshest" IRQ stack (or the trampoline stack if we came from
683 irq: label
723 * Bump the IRQ nesting count and move to the next IRQ stack.
748 irq_enter_nested: /* Nested IRQ: dump register state to stack. */
846 #define IRQ(nr) vector_ ## nr: pushq $(nr - IV_IRQS); jmp irq macro
848 IRQ( 33); IRQ( 34); IRQ( 35); IRQ( 36); IRQ( 37); IRQ( 38); IRQ( 39)
849 IRQ( 40); IRQ( 41); IRQ( 42); IRQ( 43); IRQ( 44); IRQ( 45); IRQ( 46); IRQ( 47)
850 IRQ( 48); IRQ( 49); IRQ( 50); IRQ( 51); IRQ( 52); IRQ( 53); IRQ( 54); IRQ( 55)
851 IRQ( 56); IRQ( 57); IRQ( 58); IRQ( 59); IRQ( 60); IRQ( 61); IRQ( 62); IRQ( 63)
[all …]
|
| /Zephyr-Core-3.6.0/include/zephyr/arch/arm64/ |
| D | irq.h | 18 #include <zephyr/irq.h>
38 extern void arch_irq_enable(unsigned int irq);
39 extern void arch_irq_disable(unsigned int irq);
40 extern int arch_irq_is_enabled(unsigned int irq);
43 extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio,
54 void z_soc_irq_enable(unsigned int irq);
55 void z_soc_irq_disable(unsigned int irq);
56 int z_soc_irq_is_enabled(unsigned int irq);
59 unsigned int irq, unsigned int prio, unsigned int flags);
62 void z_soc_irq_eoi(unsigned int irq);
[all …]
|
| /Zephyr-Core-3.6.0/arch/posix/core/ |
| D | irq.c | 19 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
21 posix_irq_enable(irq); in arch_irq_enable()
24 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
26 posix_irq_disable(irq); in arch_irq_disable()
29 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
31 return posix_irq_is_enabled(irq); in arch_irq_is_enabled()
40 * @param irq IRQ line number
44 * @param flags Arch-specific IRQ configuration flags
48 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in arch_irq_connect_dynamic() argument
52 posix_isr_declare(irq, (int)flags, routine, parameter); in arch_irq_connect_dynamic()
[all …]
|
| /Zephyr-Core-3.6.0/scripts/native_simulator/native/src/ |
| D | irq_ctrl.c | 7 * HW IRQ controller model
26 * irq handler
40 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
71 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
73 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
76 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
78 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
152 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
154 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
157 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
[all …]
|
| /Zephyr-Core-3.6.0/include/zephyr/arch/xtensa/ |
| D | irq.h | 87 void z_soc_irq_enable(unsigned int irq);
88 void z_soc_irq_disable(unsigned int irq);
89 int z_soc_irq_is_enabled(unsigned int irq);
91 #define arch_irq_enable(irq) z_soc_irq_enable(irq) argument
92 #define arch_irq_disable(irq) z_soc_irq_disable(irq) argument
94 #define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq) argument
97 extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
106 #define arch_irq_enable(irq) xtensa_irq_enable(irq) argument
107 #define arch_irq_disable(irq) xtensa_irq_disable(irq) argument
109 #define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq) argument
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-int-map.dtsi | 19 irq = <7>;
20 irq-prio = <2>;
24 irq = <5>;
25 irq-prio = <2>;
29 irq = <11>;
30 irq-prio = <2>;
34 irq = <35>;
35 irq-prio = <2>;
39 irq = <42>;
40 irq-prio = <2>;
[all …]
|
| /Zephyr-Core-3.6.0/soc/xtensa/dc233c/include/ |
| D | _soc_inthandlers.h | 86 int irq; in _xtensa_handle_one_int1() local
92 irq = 0; in _xtensa_handle_one_int1()
97 irq = 1; in _xtensa_handle_one_int1()
102 irq = 2; in _xtensa_handle_one_int1()
109 irq = 3; in _xtensa_handle_one_int1()
114 irq = 4; in _xtensa_handle_one_int1()
120 irq = 5; in _xtensa_handle_one_int1()
125 irq = 6; in _xtensa_handle_one_int1()
134 irq = 7; in _xtensa_handle_one_int1()
139 irq = 15; in _xtensa_handle_one_int1()
[all …]
|
| /Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/common/include/ |
| D | _soc_inthandlers.h | 122 int irq; in _xtensa_handle_one_int1() local
128 irq = 0; in _xtensa_handle_one_int1()
133 irq = 1; in _xtensa_handle_one_int1()
138 irq = 2; in _xtensa_handle_one_int1()
145 irq = 3; in _xtensa_handle_one_int1()
150 irq = 4; in _xtensa_handle_one_int1()
156 irq = 5; in _xtensa_handle_one_int1()
161 irq = 6; in _xtensa_handle_one_int1()
171 irq = 7; in _xtensa_handle_one_int1()
176 irq = 8; in _xtensa_handle_one_int1()
[all …]
|
| /Zephyr-Core-3.6.0/include/zephyr/arch/arc/v2/ |
| D | arcv2_irq_unit.h | 31 * APIs themselves are writing the IRQ_SELECT, selecting which IRQ's registers
48 int irq, in z_arc_v2_irq_unit_irq_enable_set() argument
54 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_irq_enable_set()
67 void z_arc_v2_irq_unit_int_enable(int irq) in z_arc_v2_irq_unit_int_enable() argument
69 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE); in z_arc_v2_irq_unit_int_enable()
79 void z_arc_v2_irq_unit_int_disable(int irq) in z_arc_v2_irq_unit_int_disable() argument
81 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_DISABLE); in z_arc_v2_irq_unit_int_disable()
93 bool z_arc_v2_irq_unit_int_enabled(int irq) in z_arc_v2_irq_unit_int_enabled() argument
98 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_int_enabled()
114 void z_arc_v2_irq_unit_prio_set(int irq, unsigned char prio) in z_arc_v2_irq_unit_prio_set() argument
[all …]
|
| /Zephyr-Core-3.6.0/arch/arm/core/cortex_m/ |
| D | irq_manage.c | 25 #include <zephyr/irq.h>
32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
33 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
37 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
39 NVIC_EnableIRQ((IRQn_Type)irq); in arch_irq_enable()
42 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
44 NVIC_DisableIRQ((IRQn_Type)irq); in arch_irq_disable()
47 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
49 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arch_irq_is_enabled()
61 void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_arm_irq_priority_set() argument
[all …]
|
| /Zephyr-Core-3.6.0/arch/arc/core/ |
| D | irq_manage.c | 16 * An IRQ number passed to the @a irq parameters found in this file is a
17 * number from 16 to last IRQ number on the platform.
26 #include <zephyr/irq.h>
55 /* the z_arc_firq_stack_set must be called when irq diasbled, as in z_arc_firq_stack_set()
136 * @a irq.
138 void arch_irq_enable(unsigned int irq);
144 * interrupts for the specified @a irq.
146 void arch_irq_disable(unsigned int irq);
149 * @brief Return IRQ enable state
151 * @param irq IRQ line
[all …]
|
