1/*
2 * Copyright (c) 2018 Foundries.io Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/toolchain.h>
8
9/* Imports */
10GTEXT(__initialize)
11GTEXT(_isr_wrapper)
12
13/* Exports */
14GTEXT(__start)
15
16/*
17 * Interrupts work the same way for both the RI5CY and ZERO-RISCY cores
18 * in this SoC; the only difference is the location of the vectors section
19 * on flash. We thus reuse this ivt definition for each core.
20 *
21 * On interrupt, the event unit sets pc to the address in this table
22 * at byte offset 4 * (IRQ line number).
23 *
24 * The reset, illegal instruction, ecall, and load store unit error exceptions
25 * are handled by the addresses right after the IRQ table.
26 *
27 * Note: Per RV32I restrictions, "j SOME_HANDLER" can jump within a +/- 1MiB
28 *       range. This is not a problem on this SoC: RI5CY is allocated 1MiB flash
29 *       and ZERO-RISCY is allocated 256 KiB, and these flash banks contain the
30 *       text and vectors sections, so the limits are satisfied.
31 */
32SECTION_FUNC(vectors, ivt)
33	.option norvc
34
35	/* Interrupts */
36	j _isr_wrapper	/* IRQ 0 */
37	j _isr_wrapper	/* IRQ 1 */
38	j _isr_wrapper	/* IRQ 2 */
39	j _isr_wrapper	/* IRQ 3 */
40	j _isr_wrapper	/* IRQ 4 */
41	j _isr_wrapper	/* IRQ 5 */
42	j _isr_wrapper	/* IRQ 6 */
43	j _isr_wrapper	/* IRQ 7 */
44	j _isr_wrapper	/* IRQ 8 */
45	j _isr_wrapper	/* IRQ 9 */
46	j _isr_wrapper	/* IRQ 10 */
47	j _isr_wrapper	/* IRQ 11 */
48	j _isr_wrapper	/* IRQ 12 */
49	j _isr_wrapper	/* IRQ 13 */
50	j _isr_wrapper	/* IRQ 14 */
51	j _isr_wrapper	/* IRQ 15 */
52	j _isr_wrapper	/* IRQ 16 */
53	j _isr_wrapper	/* IRQ 17 */
54	j _isr_wrapper	/* IRQ 18 */
55	j _isr_wrapper	/* IRQ 19 */
56	j _isr_wrapper	/* IRQ 20 */
57	j _isr_wrapper	/* IRQ 21 */
58	j _isr_wrapper	/* IRQ 22 */
59	j _isr_wrapper	/* IRQ 23 */
60	j _isr_wrapper	/* IRQ 24 */
61	j _isr_wrapper	/* IRQ 25 */
62	j _isr_wrapper	/* IRQ 26 */
63	j _isr_wrapper	/* IRQ 27 */
64	j _isr_wrapper	/* IRQ 28 */
65	j _isr_wrapper	/* IRQ 29 */
66	j _isr_wrapper	/* IRQ 30 */
67	j _isr_wrapper	/* IRQ 31 */
68
69	/* Exceptions */
70	j __start		/* reset */
71	j _isr_wrapper	/* illegal instruction */
72	j _isr_wrapper	/* ecall */
73	j _isr_wrapper	/* load store eunit error */
74
75SECTION_FUNC(vectors, __start)
76	/* Set mtvec to point at ivt. */
77	la t0, ivt
78	csrw 0x305, t0
79	/* Call into Zephyr initialization. */
80	tail __initialize
81