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/Zephyr-latest/tests/arch/x86/nmi/
Dtestcase.yaml5 - interrupt
6 - nmi
8 - qemu_x86_64
10 arch.interrupt.nmi:
12 - CONFIG_USERSPACE=n
13 arch.interrupt.nmi.kpti:
15 - CONFIG_TEST_USERSPACE=y
DREADME.txt1 Title: NMI registration support
5 This test verifies that NMI registration works as expected.
7 --------------------------------------------------------------------------------
18 Booting from ROM..*** Booting Zephyr OS build v2.4.0-rc1-197-g77a5f92715f7 ***
19 Running test suite nmi
21 START - test_nmi_handler
22 Testing to see interrupt handler executes properly
23 PASS - test_nmi_handler
25 Test suite nmi succeeded
/Zephyr-latest/tests/arch/arm/arm_runtime_nmi/
Dtestcase.yaml2 arch.arm.interrupt.nmi:
7 - nmi
8 - interrupt
9 - arm
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp32s2-xtensa-intmux.h4 * SPDX-License-Identifier: Apache-2.0
11 #define WIFI_MAC_NMI_SOURCE 1 /* WiFi MAC, NMI, use if MAC needs fix in NMI */
16 #define BT_BB_NMI_SOURCE 6 /* BT BB, NMI, use if BB have bug to fix in NMI */
19 #define RWBT_NMI_SOURCE 9 /* RWBT, NMI, use if RWBT has bug to fix in NMI */
20 #define RWBLE_NMI_SOURCE 10 /* RWBLE, NMI, use if RWBT has bug to fix in NMI */
33 #define GPIO_INTR_SOURCE 23 /* interrupt of GPIO, level */
34 #define GPIO_NMI_SOURCE 24 /* interrupt of GPIO, NMI */
35 #define GPIO_INTR_SOURCE2 25 /* interrupt of GPIO, level */
36 #define GPIO_NMI_SOURCE2 26 /* interrupt of GPIO, NMI */
37 #define DEDICATED_GPIO_INTR_SOURCE 27 /* interrupt of dedicated GPIO, level */
[all …]
Desp32s3-xtensa-intmux.h4 * SPDX-License-Identifier: Apache-2.0
10 #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/
11 #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI */
13 #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/
16 #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/
17 #define RWBT_INTR_SOURCE 7 /* interrupt of RWBT, level*/
18 #define RWBLE_INTR_SOURCE 8 /* interrupt of RWBLE, level*/
19 #define RWBT_NMI_SOURCE 9 /* interrupt of RWBT, NMI*/
20 #define RWBLE_NMI_SOURCE 10 /* interrupt of RWBLE, NMI*/
[all …]
Desp-xtensa-intmux.h4 * SPDX-License-Identifier: Apache-2.0
11 #define WIFI_MAC_NMI_SOURCE 1 /* WiFi MAC, NMI, use if MAC needs fix in NMI */
15 #define BT_BB_NMI_SOURCE 5 /* BT BB, NMI, use if BB have bug to fix in NMI */
18 #define RWBT_NMI_SOURCE 8 /* RWBT, NMI, use if RWBT has bug to fix in NMI */
19 #define RWBLE_NMI_SOURCE 9 /* RWBLE, NMI, use if RWBT has bug to fix in NMI */
32 #define GPIO_INTR_SOURCE 22 /* interrupt of GPIO, level */
33 #define GPIO_NMI_SOURCE 23 /* interrupt of GPIO, NMI */
65 #define SPI3_DMA_INTR_SOURCE 54 /* interrupt of SPI3 DMA, level */
80 #define MAX_INTR_SOURCE 69 /* total number of interrupt sources */
87 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
Desp-esp32c6-intmux.h4 * SPDX-License-Identifier: Apache-2.0
10 #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/
11 #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI*/
13 #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/
16 #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/
21 #define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/
24 #define EFUSE_INTR_SOURCE 14 /* interrupt of efuse, level, not likely to use*/
36 #define ASSIST_DEBUG_INTR_SOURCE 26 /* interrupt of Assist debug module, LEVEL*/
40 #define GPIO_INTR_SOURCE 30 /* interrupt of GPIO, level*/
[all …]
/Zephyr-latest/tests/arch/arm/arm_runtime_nmi/src/
Darm_runtime_nmi.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/arch/arm/nmi.h>
17 /* on v8m arch the nmi pend bit is renamed to pend nmi map it to old name */
26 printk("NMI triggered (test_handler_isr)!\n"); in nmi_test_isr()
43 * First we configure the NMI isr using z_arm_nmi_set_handler() api.
44 * After wait for some time, and set the Interrupt Control and
46 * The registered NMI isr should fire immediately.
54 /* Configure the NMI isr */ in ZTEST()
58 printk("Trigger NMI in 2s: %d s\n", i); in ZTEST()
62 /* Trigger NMI: Should fire immediately */ in ZTEST()
[all …]
/Zephyr-latest/samples/drivers/watchdog/boards/
Dcc26x2r1_launchxl.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
Dcc1352r1_launchxl.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
Dcc1352r1_sensortag.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
/Zephyr-latest/tests/arch/x86/nmi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
45 arch_curr_cpu()->id, nmi_stacks[arch_curr_cpu()->id]); in z_x86_do_kernel_nmi()
47 zassert_true(stack > (uint64_t)nmi_stacks[arch_curr_cpu()->id] && in z_x86_do_kernel_nmi()
48 stack < (uint64_t)nmi_stacks[arch_curr_cpu()->id] + in z_x86_do_kernel_nmi()
56 ZTEST(nmi, test_nmi_handler) in ZTEST() argument
58 TC_PRINT("Testing to see interrupt handler executes properly\n"); in ZTEST()
63 "Interrupt handler did not execute"); in ZTEST()
65 "Interrupt handler executed more than once! (%d)\n", in ZTEST()
69 ZTEST_SUITE(nmi, NULL, NULL, NULL, NULL, NULL);
/Zephyr-latest/drivers/watchdog/
DKconfig.smartbond4 # SPDX-License-Identifier: Apache-2.0
15 bool "NMI pre-reset interrupt enable"
20 Watchdog timer generates NMI at value 0, and WDOG (SYS)
21 reset at <= -16. Timer can be frozen/resumed using
Dwdt_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
23 * TI CC13xx/CC26xx watchdog is a 32-bit timer that runs on the MCU clock
30 * The watchdog will issue reset only on second in turn time-out (if the timer
31 * or the interrupt aren't reset after the first time-out). By default, regular
32 * interrupt is generated but platform supports also NMI (can be enabled by
33 * setting the `interrupt-nmi` boolean DT property).
58 struct wdt_cc13xx_cc26xx_data *data = dev->data; in wdt_cc13xx_cc26xx_install_timeout()
61 if (cfg->window.min != 0U || cfg->window.max == 0U) { in wdt_cc13xx_cc26xx_install_timeout()
62 return -EINVAL; in wdt_cc13xx_cc26xx_install_timeout()
69 if (cfg->window.max > WATCHDOG_MAX_RELOAD_MS) { in wdt_cc13xx_cc26xx_install_timeout()
[all …]
Dwdt_cmsdk_apb.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/arch/arm/nmi.h>
27 /* offset: 0x00c ( /w) watchdog clear interrupt register */
29 /* offset: 0x010 (r/ ) watchdog raw interrupt status register */
31 /* offset: 0x014 (r/ ) watchdog interrupt status register */
81 wdog->lock = CMSDK_APB_WDOG_UNLOCK_VALUE; in wdog_cmsdk_apb_unlock()
92 wdog->ctrl = (CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN); in wdog_cmsdk_apb_setup()
104 wdog->ctrl = ~(CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN); in wdog_cmsdk_apb_disable()
119 if (config->window.max == 0) { in wdog_cmsdk_apb_install_timeout()
120 return -EINVAL; in wdog_cmsdk_apb_install_timeout()
[all …]
/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst12 The In-Band Error Correction Code (IBECC) improves reliability by providing
15 not support the out-of-band ECC.
58 * Correctable Error (CE) - error is detected and corrected by IBECC module.
60 * Uncorrectable Error (UE) - error is detected by IBECC module and not
63 The IBECC driver provides error type for the higher-level application to
65 syndrome is not used in the IBECC driver but provided to higher-level
71 Exceptional care needs to be taken with Non Maskable Interrupt (NMI). NMI will
73 that no locking mechanism can protect code against an NMI happening. Zephyr's
75 higher-level synchronization primitives. So, you cannot share anything that is
76 "protected" by a lock with an NMI, because the protection does not work. The
[all …]
/Zephyr-latest/dts/bindings/watchdog/
Dti,cc13xx-cc26xx-watchdog.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ti,cc13xx-cc26xx-watchdog"
17 interrupt-nmi:
20 Whether the watchdog triggers a Non-Maskable Interrupt or a standard one
/Zephyr-latest/soc/nxp/kinetis/kv5x/
DKconfig.defconfig5 # SPDX-License-Identifier: Apache-2.0
10 # must be >= the highest interrupt number used
17 # 1111 1011 - Set NMI pin/interrupts to disabled.
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig.defconfig5 # SPDX-License-Identifier: Apache-2.0
10 # must be >= the highest interrupt number used
17 # 0011 1001 - Boot from Internal Flash.
18 # Set NMI pin/interrupts to disabled.
/Zephyr-latest/include/zephyr/arch/arm/
Dasm_inline_gcc.h6 * SPDX-License-Identifier: Apache-2.0
34 /* On ARMv7-M and ARMv8-M Mainline CPUs, this function prevents regular
35 * exceptions (i.e. with interrupt priority lower than or equal to
36 * _EXC_IRQ_DEFAULT_PRIO) from interrupting the CPU. NMI, Faults, SVC,
37 * and Zero Latency IRQs (if supported) may still interrupt the CPU.
39 * On ARMv6-M and ARMv8-M Baseline CPUs, this function reads the value of
41 * except NMI.
53 #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation." in arch_irq_lock()
76 /* On Cortex-M0/M0+, this enables all interrupts if they were not
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
DKconfig.defconfig3 # Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 # SPDX-License-Identifier: Apache-2.0
16 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
17 default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER
20 # must be >= the highest interrupt number used
27 # 0111 1011 - Boot from Internal Flash.
28 # Set NMI pin/interrupts to disabled.
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dentry.S4 * SPDX-License-Identifier: Apache-2.0
14 /* Disable Global Interrupt */
28 /* Set the NMI base to share with mtvec by setting CSR_MMISC_CTL */
/Zephyr-latest/arch/xtensa/core/
Dgen_vectors.py3 # SPDX-License-Identifier: Apache-2.0
9 # Takes a pre-processed (gcc -dM) core-isa.h file as its first
20 # lacks VECBASE, but the core-isa.h interface is inexplicably
36 # + XEA2 interrupt vectors are in sections named
38 # given special names. The "debug" and "NMI" interrupts (if they
39 # exist) are technically implemented as standard interrupt vectors
40 # (of a platform-dependent level), but the code for them is emitted
42 # and not a section corresponding to their interrupt level.
46 # can only back-reference immediates for MOVI/L32R instructions) as
57 # Translation for the core-isa.h vs. linker section naming conventions
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_relay.S4 * SPDX-License-Identifier: Apache-2.0
10 * @brief IRQ relay vector table and relay handler for Cortex-M0 or
11 * Armv8-M baseline SoCs
13 * In certain ARMv6-M and Armv8-M baseline cores the vector table address can
17 * This program will link into bootloader, once an interrupt is coming,
18 * the bootloader can forward the interrupt to the chainloaded image. This
57 .word __vector_relay_handler /* nmi */
Dvector_table.S2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
15 * The table is populated with all the system exception handlers. The NMI vector
36 * on the interrupt stack when CONFIG_INIT_STACKS is enabled before
37 * switching to the interrupt stack for the rest of the early boot

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