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/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
29 controller-0 {
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmi08x-accel.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 int1-map-io:
19 Bit[0]: Map Interrupt A to INT1, Accel Data Ready
20 Bit[1]: Map Interrupt B to INT1
21 Bit[2]: Map Interrupt C to INT1
23 int2-map-io:
26 Bit[0]: Map Interrupt A to INT2, Accel Data Ready
[all …]
Dbosch,bmi08x-gyro.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 int3-4-map-io:
19 Bit[0] will map the data ready interrupt on INT3
20 Bit[2] will map the fifo interrupt on INT3
21 Bit[5] will map the fifo interrupt on INT4
22 Bit[7] will enable the data ready interrupt on INT4
24 int3-4-conf-io:
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx7 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_ad0: group-ad0-map {
20 irq-prio = <2>;
21 group-mask = <0x09>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx9 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx4 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
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/Zephyr-latest/dts/riscv/
Dneorv32.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/gpio/gpio.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "neorv32-cpu", "riscv";
27 intc: interrupt-controller {
28 compatible = "riscv,cpu-intc";
29 interrupt-controller;
30 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/boards/
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ memory@40000000;
12 compatible = "mmio-sram";
16 /delete-node/ pcie@4010000000;
19 compatible = "pci-host-ecam-generic";
22 #size-cells = <0x02>;
23 #address-cells = <0x03>;
25 #interrupt-cells = <0x01>;
26 interrupt-map-mask = <0x00 0x00 0x00 0x07>;
27 interrupt-map = <
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/Zephyr-latest/drivers/sensor/bosch/bma280/
Dbma280_trigger.c4 * SPDX-License-Identifier: Apache-2.0
23 const struct bma280_config *config = dev->config; in setup_int1()
25 gpio_pin_interrupt_configure_dt(&config->int1_gpio, in setup_int1()
34 const struct bma280_config *config = dev->config; in bma280_attr_set()
37 if (!config->int1_gpio.port) { in bma280_attr_set()
38 return -ENOTSUP; in bma280_attr_set()
42 return -ENOTSUP; in bma280_attr_set()
47 slope_th = (uint64_t)val->val1 * 1000000U + (uint64_t)val->val2; in bma280_attr_set()
49 if (i2c_reg_write_byte_dt(&config->i2c, in bma280_attr_set()
53 return -EIO; in bma280_attr_set()
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/Zephyr-latest/dts/x86/intel/
Dapollo_lake.dtsi2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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/Zephyr-latest/dts/bindings/interrupt-controller/
Dnuvoton,npcx-miwu-int-map.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NPCX-MIWU group-interrupt mapping child node
6 compatible: "nuvoton,npcx-miwu-int-map"
14 child-binding:
15 description: Child node to present the mapping between MIWU group and interrupt
21 irq-prio:
25 group-mask:
28 description: group bit-mask for miwu interrupts
31 description: groups shared the same interrupt
/Zephyr-latest/drivers/gpio/
Dgpio_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
17 #include <driverlib/interrupt.h>
29 /* bits 16-18 in iocfg registers correspond to interrupt settings */
32 /* the rest are for general (non-interrupt) config */
72 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
92 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
106 return -EINVAL; in gpio_cc13xx_cc26xx_config()
187 return -ENOTSUP; in gpio_cc13xx_cc26xx_pin_interrupt_configure()
205 struct gpio_cc13xx_cc26xx_data *data = port->data; in gpio_cc13xx_cc26xx_manage_callback()
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Dgpio_andes_atcgpio100.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
35 #define REG_INTE 0x50 /* Interrupt enable reg. */
36 #define REG_IMD0 0x54 /* Interrupt mode 0 ~ 7 reg. */
37 #define REG_IMD1 0x58 /* Interrupt mode 8 ~ 15 reg. */
38 #define REG_IMD2 0x5C /* Interrupt mode 16 ~ 23 reg. */
39 #define REG_IMD3 0x60 /* Interrupt mode 24 ~ 31 reg. */
40 #define REG_ISTA 0x64 /* Interrupt status reg. */
41 #define REG_DEBE 0x70 /* De-bounce enable reg. */
42 #define REG_DEBC 0x74 /* De-Bounce control reg. */
[all …]
Dgpio_grgpio.h4 * SPDX-License-Identifier: Apache-2.0
13 uint32_t imask; /* 0x0C Interrupt mask register */
14 uint32_t ipol; /* 0x10 Interrupt polarity register */
15 uint32_t iedge; /* 0x14 Interrupt edge register */
18 uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
23 uint32_t iavail; /* 0x40 Interrupt available register */
24 uint32_t iflag; /* 0x44 Interrupt flag register */
28 uint32_t output_or; /* 0x54 I/O port output register, logical-OR */
29 uint32_t dir_or; /* 0x58 I/O port dir. register, logical-OR */
30 uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */
[all …]
Dgpio_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
33 #define GPIO_READ(r) sys_read16(config->gpio_base + (r))
34 #define GPIO_WRITE(r, v) sys_write16((v), config->gpio_base + (r))
35 #define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
49 struct gpio_nxp_s32_irq_map *map; member
86 const struct gpio_nxp_s32_config *config = dev->config; in nxp_s32_gpio_configure()
91 return -ENOTSUP; in nxp_s32_gpio_configure()
[all …]
/Zephyr-latest/drivers/sdhc/
Dintel_emmc_host.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Bit map for command Register */
18 /* Bit map for Transfer Mode Register */
31 /* Bit map for Block Size and GAP Register */
47 /* Bit Map and length details for Clock Control Register */
54 /* Bit Map for Host Control 1 Register */
179 #define GET_BITS(reg_name, start, width) ((reg_name) & (((1 << (width)) - 1) << (start)))
209 volatile uint16_t normal_int_stat; /**< Normal Interrupt Status */
210 volatile uint16_t err_int_stat; /**< Error Interrupt Status */
211 volatile uint16_t normal_int_stat_en; /**< Normal Interrupt Status Enable */
[all …]
/Zephyr-latest/boards/seagate/faze/support/
Dopenocd.cfg5 # An external debug probe must be connected to the SWD port (4-pins J2 header).
6 # Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may
10 # NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM
17 # This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
24 # 1:0 MAP System memory remap
25 # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to
27 # 0x1 User RAM Mode. Interrupt vectors are re-mapped to
29 # 0x2 User Flash Mode. Interrupt vectors are not re-mapped
31 # 31:2 - - Reserved.
32 $_TARGETNAME configure -event reset-end {
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/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10 SIUL2 EIRQ interrupt controller.
12 To route external interrupts to the WKPU interrupt controller, the GPIO
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
17 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
23 Explicitly specifying the routing of a GPIO interrupt to a particular
24 interrupt controller allows for the allocation of distinct interrupt
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso11u68/support/
Dopenocd.cfg5 # https://www.embeddedartists.com/products/lpc11u68-lpcxpresso/
9 # The on-board LPC-Link2 debug probe (based on a NXP LPC43xx MCU) provides
10 # either a CMSIS-DAP or a J-Link interface. It depends on the version of the
12 source [find interface/cmsis-dap.cfg]
15 # NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
20 # This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
27 # 1:0 MAP System memory remap
28 # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to
30 # 0x1 User RAM Mode. Interrupt vectors are re-mapped to
32 # 0x2 User Flash Mode. Interrupt vectors are not re-mapped
[all …]
/Zephyr-latest/dts/arm64/qemu/
Dqemu-virt-arm64.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dqemu-virt-a53.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 * -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_mhu.h4 * SPDX-License-Identifier: Apache-2.0
23 /* SSE 200 MHU register map structure */
25 /* (R/ ) CPU 0 Interrupt Status Register */
27 volatile uint32_t cpu0intr_set; /* ( /W) CPU 0 Interrupt Set Register */
28 volatile uint32_t cpu0intr_clr; /* ( /W) CPU 0 Interrupt Clear Register */
30 /* (R/ ) CPU 1 Interrupt Status Register */
32 volatile uint32_t cpu1intr_set; /* ( /W) CPU 1 Interrupt Set Register */
33 volatile uint32_t cpu1intr_clr; /* ( /W) CPU 1 Interrupt Clear Register */
/Zephyr-latest/include/zephyr/arch/arm64/
Dirq.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Cortex-A public interrupt handling
11 * ARM64-specific kernel interrupt handling interface.
49 * When a custom interrupt controller is specified, map the architecture
50 * interrupt control functions to the SoC layer interrupt control functions.
77 * Z_ISR_DECLARE will populate the .intList section with the interrupt's
80 * build-time.
82 * We additionally set the priority in the interrupt controller at
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1050_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "NXP MIMXRT1050-EVK board";
24 mcuboot-button0 = &user_button;
31 zephyr,uart-mcumgr = &lpuart1;
33 zephyr,shell-uart = &lpuart1;
37 /* Micron MT48LC16M16A2B4-6AIT:G */
47 nxp_parallel_lcd_connector: parallel-connector {
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