Searched full:half (Results 1 – 25 of 289) sorted by relevance
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,imx-pwm.yaml | 40 - "half-cycle"
42 - "half-and-full-cycle"
46 "half-cycle" - registers loaded on a PWM half cycle;
48 "half-and-full-cycle" - registers loaded on a PWM half & full cycle.
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| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig.vfp | 46 that supports half- and single-precision operations with 16
58 that supports half- and single-precision operations (including fused
81 that supports half-, single- and double-precision operations with 16
94 that supports half-, single- and double-precision operations
108 that supports half-, single-, double-precision operations (including
122 that supports half-, single- and double-precision operations
136 that supports half-, single-, double-precision operations (including
149 half-precision operations (half-precision extension).
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | ethernet-phy.yaml | 23 - "10BASE-T Half-Duplex"
25 - "100BASE-T Half-Duplex"
27 - "1000BASE-T Half-Duplex"
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| /Zephyr-latest/dts/bindings/i3c/ |
| D | i3c-device.yaml | 16 For I3C devices, the 3 fields are static address, first half
17 of Provisioned ID, and the second half of the Provisioned ID.
22 2. First half of the Provisioned ID contains the manufacturer
25 3. Second half of the Provisioned ID contains the combination of
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| /Zephyr-latest/doc/build/dts/ |
| D | bindings.rst | 6 A devicetree on its own is only half the story for describing hardware, as it
8 half.
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| /Zephyr-latest/dts/bindings/wifi/ |
| D | infineon,airoc-wifi-spi.yaml | 19 spi-half-duplex:
21 Use half-duplex communication; if not present, full-
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| /Zephyr-latest/scripts/tests/twister_blackbox/ |
| D | test_shuffle.py | 47 ids=['first half, 123', 'second half, 123', 'first half, 321', 'second half, 321',
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| /Zephyr-latest/include/zephyr/net/ |
| D | mii.h | 87 /** 100BASE-X half duplex capable */
91 /** 10 Mb/s half duplex capable */
95 /** 100BASE-T2 half duplex capable */
134 /** try for 10 Mb/s half duplex support */
144 /** try for 1000BASE-T half duplex support */
155 /** 1000BASE-X half-duplex capable */
159 /** 1000BASE-T half-duplex capable */
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| /Zephyr-latest/samples/boards/st/uart/single_wire/ |
| D | README.rst | 5 Use single-wire/half-duplex UART functionality of STM32 devices.
10 A simple application demonstrating how to use the single wire / half-duplex UART
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
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| /Zephyr-latest/samples/drivers/spi_flash_at45/ |
| D | sample.yaml | 50 - "Writing the first half of the test region... OK"
51 - "Writing the second half of the test region... OK"
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| /Zephyr-latest/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 17 half-duplex:
20 Enable half-duplex communication mode.
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| /Zephyr-latest/arch/xtensa/core/ |
| D | xtensa_intgen.py | 50 half = int(len(ints)/2)
53 for i in ints[0:half]:
56 emit_int_handler(ints[0:half])
58 emit_int_handler(ints[half:])
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| /Zephyr-latest/dts/bindings/dma/ |
| D | st,stm32u5-dma.yaml | 38 0x1: Half-word (16 bits)
43 0x1: Half-word (16 bits)
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| D | andestech,atcdmac300.yaml | 48 0x1: Half-word (16 bits)
56 0x1: Half-word (16 bits)
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| D | st,stm32-dmamux.yaml | 28 0x1: Half-word (16 bits)
33 0x1: Half-word (16 bits)
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| D | st,stm32-bdma.yaml | 30 0x1: Half-word (16 bits)
35 0x1: Half-word (16 bits)
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| /Zephyr-latest/samples/subsys/nvs/boards/ |
| D | nucleo_wb55rg.overlay | 11 /* Set 12KB of storage at the end of 1st half of flash (dual core constraints) */
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| /Zephyr-latest/drivers/ethernet/phy/ |
| D | phy_dm8806_priv.h | 9 /* 10 Mbit/s transfer with half duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
28 /* 10 Mbit/s transfer speed with half duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
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| /Zephyr-latest/dts/bindings/serial/ |
| D | espressif,esp32-uart.yaml | 20 Enable the hardware RS485 half duplex mode.
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| /Zephyr-latest/drivers/usb/udc/ |
| D | Kconfig.numaker | 18 Maximum number of messages the driver can queue for interrupt bottom half processing.
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| /Zephyr-latest/samples/sensor/ds18b20/boards/ |
| D | nucleo_g0b1re.overlay | 12 * b) the UART TX pin only, while the single wire half-duplex mode is enabled.
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| /Zephyr-latest/dts/bindings/w1/ |
| D | zephyr,w1-serial.yaml | 7 # the option for a "single-wire Half-duplex" mode, where the TX and RX lines
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| /Zephyr-latest/drivers/memc/ |
| D | memc_mspi_aps6404l.c | 208 LOG_DBG("Putting aps6404l to half sleep/%u", __LINE__); in memc_mspi_aps6404l_half_sleep_enter()
211 LOG_ERR("Failed to enter half sleep/%u", __LINE__); in memc_mspi_aps6404l_half_sleep_enter()
214 /** Minimum half sleep duration tHS time */ in memc_mspi_aps6404l_half_sleep_enter()
232 LOG_DBG("Waking up aps6404l from half sleep/%u", __LINE__); in memc_mspi_aps6404l_half_sleep_exit()
235 LOG_ERR("Failed to exit from half sleep/%u", __LINE__); in memc_mspi_aps6404l_half_sleep_exit()
238 /** Minimum half sleep exit CE to CLK setup time */ in memc_mspi_aps6404l_half_sleep_exit()
246 LOG_ERR("Failed to reconfigure MSPI after exiting half sleep/%u", __LINE__); in memc_mspi_aps6404l_half_sleep_exit()
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | st,stm32-nv-flash.yaml | 13 description: max erase time(millisecond) of a flash sector or page or half-page
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