Home
last modified time | relevance | path

Searched +full:half +full:- +full:duplex (Results 1 – 25 of 70) sorted by relevance

123

/Zephyr-Core-3.5.0/dts/bindings/ethernet/
Dethernet-phy.yaml1 # Copyright (c) 2021 IP-Logix Inc.
2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "ethernet-phy"
16 no-reset:
19 fixed-link:
23 - "10BASE-T Half-Duplex"
24 - "10BASE-T Full-Duplex"
25 - "100BASE-T Half-Duplex"
26 - "100BASE-T Full-Duplex"
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
[all …]
/Zephyr-Core-3.5.0/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
31 /** Auto-Negotiation Advertisement Register */
33 /** Auto-Negotiation Link Partner Ability Reg */
35 /** Auto-Negotiation Expansion Register */
37 /** Auto-Negotiation Next Page Transmit Register */
39 /** Auto-Negotiation Link Partner Received Next Page Reg */
41 /** 1000BASE-T Control Register */
43 /** 1000BASE-T Status Register */
59 /** Auto-Negotiation enable */
65 /** restart auto-negotiation */
[all …]
Dphy.h8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
31 /** 10Base-T Half-Duplex */
33 /** 10Base-T Full-Duplex */
35 /** 100Base-T Half-Duplex */
37 /** 100Base-T Full-Duplex */
39 /** 1000Base-T Half-Duplex */
41 /** 1000Base-T Full-Duplex */
110 * @retval -EIO If communication with PHY failed.
111 * @retval -ENOTSUP If not supported.
[all …]
/Zephyr-Core-3.5.0/samples/boards/stm32/uart/single_wire/
DREADME.rst1 .. zephyr:code-sample:: uart-stm32-single-wire
2 :name: STM32 single-wire UART
3 :relevant-api: uart_interface
5 Use single-wire/half-duplex UART functionality of STM32 devices.
10 A simple application demonstrating how to use the single wire / half-duplex UART
23 .. zephyr-app-commands::
24 :zephyr-app: samples/boards/stm32/uart/single_wire
32 .. code-block:: none
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: spi
13 spi-max-frequency:
17 duplex:
21 Duplex mode, full or half. By default it's always full duplex thus 0
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
[all …]
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/spi/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
17 * @name SPI duplex mode
20 * Some controllers support half duplex transfer, which results in 3-wire usage.
21 * By default, full duplex will prevail.
/Zephyr-Core-3.5.0/dts/bindings/serial/
Despressif,esp32-uart.yaml3 compatible: "espressif,esp32-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 hw-rs485-hd-mode:
20 Enable the hardware RS485 half duplex mode.
21 Overrides hw-flow-control if both are set.
Datmel,sam0-uart.yaml3 compatible: "atmel,sam0-uart"
6 - name: uart-controller.yaml
7 - name: pinctrl-device.yaml
19 clock-names:
32 collision-detection:
34 description: Enable collision detection for half-duplex mode.
45 dma-names:
51 dma-names = "tx", "rx";
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
7 include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
22 single-wire:
25 Enable the single wire half-duplex communication.
30 tx-rx-swap:
35 tx-invert:
41 rx-invert:
47 pinctrl-0:
50 pinctrl-names:
[all …]
/Zephyr-Core-3.5.0/drivers/ethernet/
DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
82 Deprecated in favor of device tree property "zephyr,random-mac-address"
90 Deprecated in favor of device tree property "local-mac-address"
130 PHY's carrier status is re-evaluated.
155 bool "Half duplex mode"
157 Set this if using half duplex when autonegotiation is disabled otherwise
158 duplex mode is full duplex
Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
[all …]
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
148 /* SPI Header for writing control transaction in half duplex mode */
150 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */
152 /* SPI Header for reading control transaction in half duplex mode */
Deth_enc424j600.c1 /* ENC424J600 Stand-alone Ethernet Controller with SPI
7 * SPDX-License-Identifier: Apache-2.0
29 const struct enc424j600_config *config = dev->config; in enc424j600_write_sbc()
40 spi_write_dt(&config->spi, &tx); in enc424j600_write_sbc()
46 const struct enc424j600_config *config = dev->config; in enc424j600_write_sfru()
62 spi_write_dt(&config->spi, &tx); in enc424j600_write_sfru()
68 const struct enc424j600_config *config = dev->config; in enc424j600_read_sfru()
90 if (!spi_transceive_dt(&config->spi, &tx, &rx)) { in enc424j600_read_sfru()
101 const struct enc424j600_config *config = dev->config; in enc424j600_modify_sfru()
117 spi_write_dt(&config->spi, &tx); in enc424j600_modify_sfru()
[all …]
/Zephyr-Core-3.5.0/samples/sensor/ds18b20/boards/
Dnucleo_g0b1re.overlay4 * SPDX-License-Identifier: Apache-2.0
12 * b) the UART TX pin only, while the single wire half-duplex mode is enabled.
13 * An external pull-up should be added anyways.
19 drive-open-drain;
20 bias-pull-up;
/Zephyr-Core-3.5.0/dts/bindings/w1/
Dzephyr,w1-serial.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Properties for the serial 1-Wire master driver:
7 # the option for a "single-wire Half-duplex" mode, where the TX and RX lines
9 # needs to be allocated for the 1-Wire communication.
11 description: 1-Wire master over Zephyr uart
13 compatible: "zephyr,w1-serial"
15 include: [uart-device.yaml, w1-master.yaml]
/Zephyr-Core-3.5.0/doc/connectivity/networking/api/
Dethernet.rst28 * Half/full duplex
33 * :ref:`Priority queues <traffic-class-support>`
39 see what is supported by ``net iface`` net-shell command. It will print
/Zephyr-Core-3.5.0/drivers/serial/
Duart_stm32.h2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
36 /* switch to enable single wire / half duplex feature */
59 /* Device defined as wake-up source */
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
41 * CPOL/CPHA = 0/0 --> SPI_MODE_0
42 * CPOL/CPHA = 0/1 --> SPI_MODE_1
43 * CPOL/CPHA = 1/0 --> SPI_MODE_2
44 * CPOL/CPHA = 1/1 --> SPI_MODE_3
57 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
58 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
61 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
65 if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) { in spi_numaker_configure()
67 return -ENOTSUP; in spi_numaker_configure()
[all …]
Dspi_bitbang.c2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
34 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
36 return -ENOTSUP; in spi_bitbang_configure()
39 if (config->operation & (SPI_TRANSFER_LSB | SPI_LINES_DUAL in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure()
49 return -ENOTSUP; in spi_bitbang_configure()
52 data->bits = bits; in spi_bitbang_configure()
53 data->dfs = ((data->bits - 1) / 8) + 1; in spi_bitbang_configure()
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
84 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
Dspi_litespi.c4 * SPDX-License-Identifier: Apache-2.0
20 if (config->slave != 0) { in spi_config()
21 if (config->slave >= SPI_MAX_CS_SIZE) { in spi_config()
23 return -ENOTSUP; in spi_config()
25 cs = (uint8_t)(config->slave); in spi_config()
28 if (config->operation & SPI_HALF_DUPLEX) { in spi_config()
29 LOG_ERR("Half-duplex not supported"); in spi_config()
30 return -ENOTSUP; in spi_config()
33 if (SPI_WORD_SIZE_GET(config->operation) != 8) { in spi_config()
35 return -ENOTSUP; in spi_config()
[all …]
/Zephyr-Core-3.5.0/doc/hardware/peripherals/
Dw1.rst3 1-Wire Bus
9 1-Wire is a low speed half-duplex serial bus using only a single wire plus
11 Similarly to I2C, 1-Wire uses a bidirectional open-collector data line,
14 The 1-Wire bus supports longer bus lines than I2C, while it reaches speeds of up
23 .. figure:: 1-Wire_bus_topology.drawio.svg
25 :alt: 1-Wire bus topology
27 A typical 1-Wire bus topology
30 .. _w1-master-api:
35 Zephyr's 1-Wire Master API is used to interact with 1-Wire slave devices like
42 It is the only hardware-dependent layer in Zephyr.
[all …]

123