1 /* 2 * Copyright (c) 2016 Piotr Mienkowski 3 * Copyright 2022 NXP 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /** @file 9 * @brief Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_NET_MII_H_ 13 #define ZEPHYR_INCLUDE_NET_MII_H_ 14 15 /** 16 * @brief Ethernet MII (media independent interface) functions 17 * @defgroup ethernet_mii Ethernet MII Support Functions 18 * @ingroup ethernet 19 * @{ 20 */ 21 22 /* MII management registers */ 23 /** Basic Mode Control Register */ 24 #define MII_BMCR 0x0 25 /** Basic Mode Status Register */ 26 #define MII_BMSR 0x1 27 /** PHY ID 1 Register */ 28 #define MII_PHYID1R 0x2 29 /** PHY ID 2 Register */ 30 #define MII_PHYID2R 0x3 31 /** Auto-Negotiation Advertisement Register */ 32 #define MII_ANAR 0x4 33 /** Auto-Negotiation Link Partner Ability Reg */ 34 #define MII_ANLPAR 0x5 35 /** Auto-Negotiation Expansion Register */ 36 #define MII_ANER 0x6 37 /** Auto-Negotiation Next Page Transmit Register */ 38 #define MII_ANNPTR 0x7 39 /** Auto-Negotiation Link Partner Received Next Page Reg */ 40 #define MII_ANLPRNPR 0x8 41 /** 1000BASE-T Control Register */ 42 #define MII_1KTCR 0x9 43 /** 1000BASE-T Status Register */ 44 #define MII_1KSTSR 0xa 45 /** MMD Access Control Register */ 46 #define MII_MMD_ACR 0xd 47 /** MMD Access Address Data Register */ 48 #define MII_MMD_AADR 0xe 49 /** Extended Status Register */ 50 #define MII_ESTAT 0xf 51 52 /* Basic Mode Control Register (BMCR) bit definitions */ 53 /** PHY reset */ 54 #define MII_BMCR_RESET (1 << 15) 55 /** enable loopback mode */ 56 #define MII_BMCR_LOOPBACK (1 << 14) 57 /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ 58 #define MII_BMCR_SPEED_LSB (1 << 13) 59 /** Auto-Negotiation enable */ 60 #define MII_BMCR_AUTONEG_ENABLE (1 << 12) 61 /** power down mode */ 62 #define MII_BMCR_POWER_DOWN (1 << 11) 63 /** isolate electrically PHY from MII */ 64 #define MII_BMCR_ISOLATE (1 << 10) 65 /** restart auto-negotiation */ 66 #define MII_BMCR_AUTONEG_RESTART (1 << 9) 67 /** full duplex mode */ 68 #define MII_BMCR_DUPLEX_MODE (1 << 8) 69 /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ 70 #define MII_BMCR_SPEED_MSB (1 << 6) 71 /** Link Speed Field */ 72 #define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13) 73 /** select speed 10 Mb/s */ 74 #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13) 75 /** select speed 100 Mb/s */ 76 #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13) 77 /** select speed 1000 Mb/s */ 78 #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13) 79 80 /* Basic Mode Status Register (BMSR) bit definitions */ 81 /** 100BASE-T4 capable */ 82 #define MII_BMSR_100BASE_T4 (1 << 15) 83 /** 100BASE-X full duplex capable */ 84 #define MII_BMSR_100BASE_X_FULL (1 << 14) 85 /** 100BASE-X half duplex capable */ 86 #define MII_BMSR_100BASE_X_HALF (1 << 13) 87 /** 10 Mb/s full duplex capable */ 88 #define MII_BMSR_10_FULL (1 << 12) 89 /** 10 Mb/s half duplex capable */ 90 #define MII_BMSR_10_HALF (1 << 11) 91 /** 100BASE-T2 full duplex capable */ 92 #define MII_BMSR_100BASE_T2_FULL (1 << 10) 93 /** 100BASE-T2 half duplex capable */ 94 #define MII_BMSR_100BASE_T2_HALF (1 << 9) 95 /** extend status information in reg 15 */ 96 #define MII_BMSR_EXTEND_STATUS (1 << 8) 97 /** PHY accepts management frames with preamble suppressed */ 98 #define MII_BMSR_MF_PREAMB_SUPPR (1 << 6) 99 /** Auto-negotiation process completed */ 100 #define MII_BMSR_AUTONEG_COMPLETE (1 << 5) 101 /** remote fault detected */ 102 #define MII_BMSR_REMOTE_FAULT (1 << 4) 103 /** PHY is able to perform Auto-Negotiation */ 104 #define MII_BMSR_AUTONEG_ABILITY (1 << 3) 105 /** link is up */ 106 #define MII_BMSR_LINK_STATUS (1 << 2) 107 /** jabber condition detected */ 108 #define MII_BMSR_JABBER_DETECT (1 << 1) 109 /** extended register capabilities */ 110 #define MII_BMSR_EXTEND_CAPAB (1 << 0) 111 112 /* Auto-negotiation Advertisement Register (ANAR) bit definitions */ 113 /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */ 114 /** next page */ 115 #define MII_ADVERTISE_NEXT_PAGE (1 << 15) 116 /** link partner acknowledge response */ 117 #define MII_ADVERTISE_LPACK (1 << 14) 118 /** remote fault */ 119 #define MII_ADVERTISE_REMOTE_FAULT (1 << 13) 120 /** try for asymmetric pause */ 121 #define MII_ADVERTISE_ASYM_PAUSE (1 << 11) 122 /** try for pause */ 123 #define MII_ADVERTISE_PAUSE (1 << 10) 124 /** try for 100BASE-T4 support */ 125 #define MII_ADVERTISE_100BASE_T4 (1 << 9) 126 /** try for 100BASE-X full duplex support */ 127 #define MII_ADVERTISE_100_FULL (1 << 8) 128 /** try for 100BASE-X support */ 129 #define MII_ADVERTISE_100_HALF (1 << 7) 130 /** try for 10 Mb/s full duplex support */ 131 #define MII_ADVERTISE_10_FULL (1 << 6) 132 /** try for 10 Mb/s half duplex support */ 133 #define MII_ADVERTISE_10_HALF (1 << 5) 134 /** Selector Field */ 135 #define MII_ADVERTISE_SEL_MASK (0x1F << 0) 136 #define MII_ADVERTISE_SEL_IEEE_802_3 0x01 137 138 /* 1000BASE-T Control Register bit definitions */ 139 /** try for 1000BASE-T full duplex support */ 140 #define MII_ADVERTISE_1000_FULL (1 << 9) 141 /** try for 1000BASE-T half duplex support */ 142 #define MII_ADVERTISE_1000_HALF (1 << 8) 143 144 #define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\ 145 MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\ 146 MII_ADVERTISE_SEL_IEEE_802_3) 147 148 /* Extended Status Register bit definitions */ 149 /** 1000BASE-X full-duplex capable */ 150 #define MII_ESTAT_1000BASE_X_FULL (1 << 15) 151 /** 1000BASE-X half-duplex capable */ 152 #define MII_ESTAT_1000BASE_X_HALF (1 << 14) 153 /** 1000BASE-T full-duplex capable */ 154 #define MII_ESTAT_1000BASE_T_FULL (1 << 13) 155 /** 1000BASE-T half-duplex capable */ 156 #define MII_ESTAT_1000BASE_T_HALF (1 << 12) 157 158 /** 159 * @} 160 */ 161 162 #endif /* ZEPHYR_INCLUDE_NET_MII_H_ */ 163
