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/Zephyr-Core-3.4.0/tests/drivers/build_all/gpio/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
/Zephyr-Core-3.4.0/dts/arm/infineon/psoc6/psoc6_04/
Dpsoc6_04.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-Core-3.4.0/dts/arm/ti/
Dlm3s6965.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
7 #address-cells = <1>;
8 #size-cells = <0>;
12 compatible = "arm,cortex-m3";
18 compatible = "mmio-sram";
22 sysclk: system-clock {
23 compatible = "fixed-clock";
24 clock-frequency = <12000000>;
25 #clock-cells = <0>;
[all …]
/Zephyr-Core-3.4.0/dts/arm/infineon/psoc6/psoc6_01/
Dpsoc6_01.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40250000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-Core-3.4.0/dts/arm/infineon/psoc6/psoc6_03/
Dpsoc6_03.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32l23x/
Dgd32l23x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/clock/gd32l23x-clocks.h>
12 #include <zephyr/dt-bindings/reset/gd32l23x.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m23";
22 clock-frequency = <DT_FREQ_M(64)>;
[all …]
/Zephyr-Core-3.4.0/dts/arm/infineon/psoc6/psoc6_02/
Dpsoc6_02.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-Core-3.4.0/dts/arm/silabs/
Defm32hg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv6-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
10 zephyr,flash-controller = &msc;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-m0+";
24 compatible = "mmio-sram";
28 msc: flash-controller@400c0000 {
[all …]
Defm32_jg_pg_12b.dtsi4 * Copyright (c) 2021 T-Mobile USA, Inc.
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
18 zephyr,flash-controller = &msc;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 compatible = "mmio-sram";
[all …]
Defr32fg1p.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/pwm/pwm.h>
11 zephyr,flash-controller = &msc;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m4f";
25 compatible = "mmio-sram";
[all …]
Defr32mg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/pwm/pwm.h>
12 zephyr,flash-controller = &msc;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m4f";
26 compatible = "mmio-sram";
[all …]
Defm32_pg_1b.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
14 zephyr,flash-controller = &msc;
18 #address-cells = <1>;
19 #size-cells = <0>;
24 compatible = "mmio-sram";
28 msc: flash-controller@400e0000 {
29 compatible = "silabs,gecko-flash-controller";
[all …]
Defm32wg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
10 zephyr,flash-controller = &msc;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
24 compatible = "mmio-sram";
28 msc: flash-controller@400c0000 {
[all …]
Defr32mg24.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/pinctrl/gecko-pinctrl.h>
12 #include <dt-bindings/adc/adc.h>
16 zephyr,flash-controller = &msc;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-m33";
[all …]
Defm32gg11b.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
16 zephyr,flash-controller = &msc;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
30 compatible = "mmio-sram";
34 msc: flash-controller@40000000 {
[all …]
/Zephyr-Core-3.4.0/drivers/gpio/
Dgpio_xlnx_ps.c2 * Xilinx Processor System MIO / EMIO GPIO controller driver
6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
30 * @brief Initialize a Xilinx PS GPIO controller parent device
32 * Initialize a Xilinx PS GPIO controller parent device, whose task it is
33 * to handle the IRQ line of each controller instance, while the configuration,
34 * status and data acquisition of each MIO / EMIO GPIO pin associated with
35 * the parent controller instance is handled via the respective GPIO pin
38 * @param dev Pointer to the PS GPIO controller's device.
[all …]
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f3x0.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/gd32f3x0.h>
12 #include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f3x0.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(108)>;
[all …]
/Zephyr-Core-3.4.0/dts/arm/nuvoton/
Dm48x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
24 compatible = "mmio-sram";
28 compatible = "serial-flash";
29 erase-block-size = <4096>;
30 write-block-size = <1>;
[all …]
Dnpcx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/sensor/npcx_tach.h>
21 #address-cells = <1>;
[all …]
/Zephyr-Core-3.4.0/dts/bindings/gpio/
Dgpio-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for GPIO controllers
7 "gpio-controller":
10 description: Convey's this node is a GPIO controller
11 "#gpio-cells":
14 description: Number of items to expect in a GPIO specifier
19 This property indicates the number of in-use slots of available slots
28 gpio-reserved-ranges:
31 If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
36 For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
[all …]
Dnuvoton,nct38xx-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nuvoton NCT38XX series I2C-based GPIO expander
10 #address-cells = <1>;
11 #size-cells = <0>;
12 compatible = "nuvoton,nct38xx-gpio";
15 gpio@0 {
16 compatible = "nuvoton,nct38xx-gpio-port";
18 gpio-controller;
19 #gpio-cells = <2>;
25 gpio@1 {
[all …]
Dnxp,lpc11u6x-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP LPC11U6X GPIO node
6 compatible: "nxp,lpc11u6x-gpio"
8 include: [gpio-controller.yaml, base.yaml]
17 "#gpio-cells":
23 description: index of the first GPIO for this port.
33 controller associated with the GPIO controller.
35 gpio-cells:
36 - pin
37 - flags
Dxlnx,ps-gpio-bank.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
10 a bank of the MIO/EMIO GPIO controller integrated in the Processor
13 compatible: "xlnx,ps-gpio-bank"
15 include: [gpio-controller.yaml, base.yaml]
21 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
/Zephyr-Core-3.4.0/dts/arm/cypress/
Dpsoc6.dtsi3 * Copyright (c) 2020-2021, ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "psoc6-pinctrl.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
25 compatible = "arm,cortex-m4f";
30 flash-controller@40250000 {
31 compatible = "cypress,psoc6-flash-controller";
[all …]
/Zephyr-Core-3.4.0/dts/riscv/microchip/
Dmpfs-icicle.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]

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