1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <mem.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-m0+";
18			reg = <0>;
19		};
20		cpu@1 {
21			device_type = "cpu";
22			compatible = "arm,cortex-m4f";
23			reg = <1>;
24		};
25	};
26
27	flash-controller@40250000 {
28		compatible = "infineon,cat1-flash-controller";
29		reg = < 0x40250000 0x10000 >;
30		#address-cells = <1>;
31		#size-cells = <1>;
32
33		flash0: flash@10000000 {
34			compatible = "soc-nv-flash";
35			reg = <0x10000000 0x100000>;
36			write-block-size = <512>;
37			erase-block-size = <512>;
38		};
39		flash1: flash@14000000 {
40			compatible = "soc-nv-flash";
41			reg = <0x14000000 0x8000>;
42			write-block-size = <512>;
43			erase-block-size = <512>;
44		};
45	};
46
47	sram0: memory@8000000 {
48		compatible = "mmio-sram";
49		reg = <0x8000000 0x48000>;
50	};
51
52	soc {
53		pinctrl: pinctrl@40310000 {
54			compatible = "infineon,cat1-pinctrl";
55			reg = <0x40310000 0x20000>;
56			#address-cells = <1>;
57			#size-cells = <0>;
58
59			hsiom: hsiom@40310000 {
60				compatible = "infineon,cat1-hsiom";
61				reg = <0x40310000 0x4000>;
62				interrupts = <15 6>, <16 6>;
63				status = "disabled";
64			};
65
66			gpio_prt0: gpio@40320000 {
67				compatible = "infineon,cat1-gpio";
68				reg = <0x40320000 0x80>;
69				interrupts = <0 6>;
70				gpio-controller;
71				ngpios = <6>;
72				status = "disabled";
73				#gpio-cells = <2>;
74			};
75			gpio_prt1: gpio@40320080 {
76				compatible = "infineon,cat1-gpio";
77				reg = <0x40320080 0x80>;
78				interrupts = <1 6>;
79				gpio-controller;
80				ngpios = <6>;
81				status = "disabled";
82				#gpio-cells = <2>;
83			};
84			gpio_prt2: gpio@40320100 {
85				compatible = "infineon,cat1-gpio";
86				reg = <0x40320100 0x80>;
87				interrupts = <2 6>;
88				gpio-controller;
89				ngpios = <8>;
90				status = "disabled";
91				#gpio-cells = <2>;
92			};
93			gpio_prt3: gpio@40320180 {
94				compatible = "infineon,cat1-gpio";
95				reg = <0x40320180 0x80>;
96				interrupts = <3 6>;
97				gpio-controller;
98				ngpios = <6>;
99				status = "disabled";
100				#gpio-cells = <2>;
101			};
102			gpio_prt4: gpio@40320200 {
103				compatible = "infineon,cat1-gpio";
104				reg = <0x40320200 0x80>;
105				interrupts = <4 6>;
106				gpio-controller;
107				ngpios = <2>;
108				status = "disabled";
109				#gpio-cells = <2>;
110			};
111			gpio_prt5: gpio@40320280 {
112				compatible = "infineon,cat1-gpio";
113				reg = <0x40320280 0x80>;
114				interrupts = <5 6>;
115				gpio-controller;
116				ngpios = <8>;
117				status = "disabled";
118				#gpio-cells = <2>;
119			};
120			gpio_prt6: gpio@40320300 {
121				compatible = "infineon,cat1-gpio";
122				reg = <0x40320300 0x80>;
123				interrupts = <6 6>;
124				gpio-controller;
125				ngpios = <8>;
126				status = "disabled";
127				#gpio-cells = <2>;
128			};
129			gpio_prt7: gpio@40320380 {
130				compatible = "infineon,cat1-gpio";
131				reg = <0x40320380 0x80>;
132				interrupts = <7 6>;
133				gpio-controller;
134				ngpios = <8>;
135				status = "disabled";
136				#gpio-cells = <2>;
137			};
138			gpio_prt8: gpio@40320400 {
139				compatible = "infineon,cat1-gpio";
140				reg = <0x40320400 0x80>;
141				interrupts = <8 6>;
142				gpio-controller;
143				ngpios = <8>;
144				status = "disabled";
145				#gpio-cells = <2>;
146			};
147			gpio_prt9: gpio@40320480 {
148				compatible = "infineon,cat1-gpio";
149				reg = <0x40320480 0x80>;
150				interrupts = <9 6>;
151				gpio-controller;
152				ngpios = <8>;
153				status = "disabled";
154				#gpio-cells = <2>;
155			};
156			gpio_prt10: gpio@40320500 {
157				compatible = "infineon,cat1-gpio";
158				reg = <0x40320500 0x80>;
159				interrupts = <10 6>;
160				gpio-controller;
161				ngpios = <8>;
162				status = "disabled";
163				#gpio-cells = <2>;
164			};
165			gpio_prt11: gpio@40320580 {
166				compatible = "infineon,cat1-gpio";
167				reg = <0x40320580 0x80>;
168				interrupts = <11 6>;
169				gpio-controller;
170				ngpios = <8>;
171				status = "disabled";
172				#gpio-cells = <2>;
173			};
174			gpio_prt12: gpio@40320600 {
175				compatible = "infineon,cat1-gpio";
176				reg = <0x40320600 0x80>;
177				interrupts = <12 6>;
178				gpio-controller;
179				ngpios = <8>;
180				status = "disabled";
181				#gpio-cells = <2>;
182			};
183			gpio_prt13: gpio@40320680 {
184				compatible = "infineon,cat1-gpio";
185				reg = <0x40320680 0x80>;
186				interrupts = <13 6>;
187				gpio-controller;
188				ngpios = <8>;
189				status = "disabled";
190				#gpio-cells = <2>;
191			};
192			gpio_prt14: gpio@40320700 {
193				compatible = "infineon,cat1-gpio";
194				reg = <0x40320700 0x80>;
195				interrupts = <14 6>;
196				gpio-controller;
197				ngpios = <2>;
198				status = "disabled";
199				#gpio-cells = <2>;
200			};
201		};
202		uid: device_uid@16000600 {
203			compatible = "infineon,cat1-uid";
204			reg = <0x16000600 0xb>;
205			status = "disabled";
206		};
207
208		adc0: adc@411f0000 {
209			compatible = "infineon,cat1-adc";
210			reg = <0x411f0000 0x10000>;
211			interrupts = <138 6>;
212			status = "disabled";
213			#io-channel-cells = <1>;
214		};
215
216		scb0: scb@40610000 {
217			compatible = "infineon,cat1-scb";
218			reg = <0x40610000 0x10000>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupts = <41 6>;
222			status = "disabled";
223		};
224		scb1: scb@40620000 {
225			compatible = "infineon,cat1-scb";
226			reg = <0x40620000 0x10000>;
227			#address-cells = <1>;
228			#size-cells = <0>;
229			interrupts = <42 6>;
230			status = "disabled";
231		};
232		scb2: scb@40630000 {
233			compatible = "infineon,cat1-scb";
234			reg = <0x40630000 0x10000>;
235			#address-cells = <1>;
236			#size-cells = <0>;
237			interrupts = <43 6>;
238			status = "disabled";
239		};
240		scb3: scb@40640000 {
241			compatible = "infineon,cat1-scb";
242			reg = <0x40640000 0x10000>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupts = <44 6>;
246			status = "disabled";
247		};
248		scb4: scb@40650000 {
249			compatible = "infineon,cat1-scb";
250			reg = <0x40650000 0x10000>;
251			#address-cells = <1>;
252			#size-cells = <0>;
253			interrupts = <45 6>;
254			status = "disabled";
255		};
256		scb5: scb@40660000 {
257			compatible = "infineon,cat1-scb";
258			reg = <0x40660000 0x10000>;
259			#address-cells = <1>;
260			#size-cells = <0>;
261			interrupts = <46 6>;
262			status = "disabled";
263		};
264		scb6: scb@40670000 {
265			compatible = "infineon,cat1-scb";
266			reg = <0x40670000 0x10000>;
267			#address-cells = <1>;
268			#size-cells = <0>;
269			interrupts = <47 6>;
270			status = "disabled";
271		};
272		scb7: scb@40680000 {
273			compatible = "infineon,cat1-scb";
274			reg = <0x40680000 0x10000>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			interrupts = <48 6>;
278			status = "disabled";
279		};
280		scb8: scb@40690000 {
281			compatible = "infineon,cat1-scb";
282			reg = <0x40690000 0x10000>;
283			#address-cells = <1>;
284			#size-cells = <0>;
285			interrupts = <18 6>;
286			status = "disabled";
287		};
288
289		timer0: timer@40260200 {
290			compatible = "infineon,cat1-timer";
291			reg = <0x40260200 0x40>;
292			interrupts = <19 6>;
293			status = "disabled";
294		};
295		timer1: timer@40260240 {
296			compatible = "infineon,cat1-timer";
297			reg = <0x40260240 0x40>;
298			interrupts = <20 6>;
299			status = "disabled";
300		};
301
302		watchdog0: watchdog@40260180 {
303			compatible = "infineon,cat1-watchdog";
304			reg = <0x40260180 0xc>;
305			interrupts = <22 6>;
306			status = "disabled";
307		};
308
309		bluetooth: bless {
310			compatible = "infineon,cat1-bless-hci";
311			interrupts = <24 1>;
312			status = "disabled";
313		};
314	};
315};
316