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/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7-pll-clock.yaml69 fracn:
72 PLLx FRACN value
Dst,stm32u5-pll-clock.yaml75 fracn:
78 PLLx FRACN value
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dpll_hsi_fracn_160.overlay22 fracn = <0>;
Dpll_hse_fracn_160.overlay28 fracn = <602>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dpll_hsi_fracn_550.overlay24 fracn = <3072>;
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h171 #define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
172 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
209 #define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
210 #define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
227 #define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
228 #define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
/Zephyr-latest/doc/releases/
Drelease-notes-4.0.rst459 * STM32H7: PLL FRACN can now be configured (see :dtcompatible:`st,stm32h7-pll-clock`)
Drelease-notes-3.5.rst1866 * new property: ``fracn``