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/Zephyr-latest/dts/bindings/serial/
Dinfineon,xmc4xxx-uart.yaml3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
[all …]
Dzephyr,uart-emul.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,uart-emul"
8 include: uart-controller.yaml
11 tx-fifo-size:
15 Size of the virtual UART TX FIFO
17 rx-fifo-size:
21 Size of the virtual UART RX FIFO
26 Connects TX to RX internally creating a loop back connection. Useful
29 latch-buffer-size:
33 Size of the virtual UART latch buffer.
Dzephyr,nus-uart.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,nus-uart"
9 tx-fifo-size:
13 Size of the virtual UART TX FIFO
15 rx-fifo-size:
19 Size of the virtual UART RX FIFO
Dzephyr,cdc-acm-uart.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,cdc-acm-uart"
8 include: uart-controller.yaml
10 on-bus: usb
13 tx-fifo-size:
17 Size of the virtual CDC ACM UART TX FIFO
19 rx-fifo-size:
23 Size of the virtual CDC ACM UART RX FIFO
/Zephyr-latest/dts/bindings/spi/
Dnxp,dspi.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
26 sck-pcs-delay:
32 transfer-delay:
38 pinctrl-0:
41 nxp,rx-tx-chn-share:
43 description: If the edma channel shared with tx and rx
48 ctar register selection range form 0-1 for master mode, 0 for slave mode
50 sample-point:
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Dxlnx,xps-spi-2.00.a.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "xlnx,xps-spi-2.00.a"
8 include: spi-controller.yaml
11 # https://github.com/Xilinx/device-tree-xlnx
20 xlnx,num-ss-bits:
24 - 1
25 - 2
26 - 3
27 - 4
31 xlnx,num-transfer-bits:
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/Zephyr-latest/tests/drivers/uart/uart_emul/
Duart_emul.overlay4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
16 euart1: uart-dummy-bus {
17 compatible = "zephyr,uart-emul";
19 current-speed = <0>;
20 rx-fifo-size = <256>;
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/Zephyr-latest/tests/subsys/logging/log_backend_uart/
Dmulti.overlay4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,log-uart = &log_uarts;
13 compatible = "zephyr,log-uart";
17 euart0: uart-emul0 {
18 compatible = "zephyr,uart-emul";
20 current-speed = <0>;
21 rx-fifo-size = <256>;
22 tx-fifo-size = <256>;
25 euart1: uart-emul1 {
26 compatible = "zephyr,uart-emul";
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Dsingle.overlay4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,log-uart = &log_uarts;
13 compatible = "zephyr,log-uart";
17 euart0: uart-emul0 {
18 compatible = "zephyr,uart-emul";
20 current-speed = <0>;
21 rx-fifo-size = <256>;
22 tx-fifo-size = <256>;
/Zephyr-latest/drivers/ethernet/
DKconfig.nxp_s32_gmac1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
22 must be a multiple of TX FIFO block size.
25 int "TX ring data buffer size"
29 Size, in bytes, of the TX data buffer. The size must be big enough to
34 int "RX ring length"
38 Length of the RX ring. ETH_NXP_S32_RX_RING_BUF_SIZE * ETH_NXP_S32_RX_RING_LEN
39 must be a multiple of RX FIFO block size.
42 int "RX ring data buffer size"
46 Size, in bytes, of the RX data buffer. The size must be big enough to
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/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Dxmc45_relax_kit.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
7 current-speed = <921600>;
8 pinctrl-0 = <&uart_tx_p5_0_u2c0 &uart_rx_p5_1_u2c0>;
9 pinctrl-names = "default";
10 input-src = "DX0G";
12 interrupt-names = "tx", "rx";
14 dma-names = "tx", "rx";
15 fifo-start-offset = <0>;
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Dxmc47_relax_kit.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
9 /delete-property/ scl-src;
10 /delete-property/ sda-src;
12 current-speed = <921600>;
14 interrupt-names = "tx", "rx";
16 dma-names = "tx", "rx";
17 pinctrl-0 = <&uart_tx_p3_15_u1c1 &uart_rx_p3_14_u1c1>;
18 pinctrl-names = "default";
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/Zephyr-latest/dts/bindings/usb/
Drenesas,smartbond-usbd.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-usbd"
8 include: usb-ep.yaml
11 dma-min-transfer-size:
14 Minimum transfer size required to engage DMA.
16 ep-out-buf-size:
20 Buffer size for OUT end points 0-3.
22 fifo-read-threshold:
25 RX FIFO is 64 bytes. When endpoint size is greater then 64,
26 FIFO warning interrupt is enabled to allow read incoming data
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/Zephyr-latest/drivers/can/
DKconfig.xmc4xxx3 # SPDX-License-Identifier: Apache-2.0
20 Defines the array size of transmit callback pointers and semaphores,
24 int "Number of CAN messages allocated to each RX FIFO"
28 Defines the number of CAN messages in each RX FIFO. A separate RX FIFO
29 is created for each RX filter.
DKconfig.mcp251xfd5 # SPDX-License-Identifier: Apache-2.0
23 Defines the array size of transmit callback pointers and semaphores,
27 int "Number of CAN messages in the RX fifo"
31 Defines the number of CAN messages in the RX fifo.
34 int "Stack size for interrupt handler"
37 Size of the stack used for internal thread which is ran for
/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Dxmc47_relax_kit.dts2 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include "xmc47_relax_kit-pinctrl.dtsi"
22 die-temp0 = &die_temp;
23 pwm-led0 = &pwm_led1;
29 compatible = "gpio-leds";
40 compatible = "pwm-leds";
55 zephyr,shell-uart = &usic0ch0;
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
8 This DMA controller includes FIFO control registers.
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
[all …]
/Zephyr-latest/tests/subsys/shell/shell_backend_uart/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul0 {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
/Zephyr-latest/samples/subsys/logging/logger/
Dbt.overlay4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "zephyr,nus-uart";
14 rx-fifo-size = <1024>;
15 tx-fifo-size = <1024>;
/Zephyr-latest/snippets/nus-console/
Dnus-console.overlay4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
/Zephyr-latest/samples/subsys/shell/shell_module/
Dbt.overlay4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
/Zephyr-latest/dts/bindings/dai/
Dnxp,dai-esai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-esai"
13 dai-index:
21 tx-fifo-watermark:
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 the TX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
29 rx-fifo-watermark:
32 Use this property to specify the watermark value for the RX
33 FIFO. This values needs to be in FIFO words (NOT BYTES). This
36 the RX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
[all …]
Dnxp,dai-sai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-sai"
8 include: [base.yaml, pinctrl-device.yaml]
13 mclk-is-output:
21 rx-fifo-watermark:
25 FIFO. This value needs to be in FIFO words (NOT BYTES). This
28 tx-fifo-watermark:
31 Use this property to specify the watermark value for the RX
32 FIFO. This value needs to be in FIFO words (NOT BYTES). This
37 fifo-depth:
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/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
28 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
40 Make sure that you set correct value of the ``dcache-alignment``.
46 .. code-block:: devicetree
48 reserved-memory {
53 rx: memory@20078000 {
60 compatible = "zephyr,ipc-icmsg";
61 dcache-alignment = <32>;
62 tx-region = <&tx>;
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