Searched full:fed (Results 1 – 25 of 50) sorted by relevance
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19 configuration. The UARTs are fed a master clock which is fed into a PLL which
41 Divides the kernel clock giving the time quanta clock that is fed to the
40 Divides the kernel clock giving the time quanta clock that is fed to the FDCAN core
26 request status of all devices fed by the regulator.
11 malfunctions. Once initialized, the watchdog timer has to be restarted ("fed")
20 * just the final variant include in code fed to compiler/assembler.
109 * watchdog needs to be fed) or for a channel that has been deleted, in task_wdt_trigger()111 * fed right after that new timeout is scheduled). in task_wdt_trigger()
164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
46 voltage will be fed from a regulator that provides a fixed voltage
62 The Renode-emulated LiteX/VexRiscv board is fed data that the
98 * @param channel_id Index of the fed channel as returned by task_wdt_add().
147 LOG_DBG("Fed the watchdog"); in wdt_ambiq_feed()
117 LOG_DBG("Fed the watchdog"); in mcux_wdog_feed()
130 LOG_DBG("Fed the watchdog"); in mcux_wdog_feed()
147 LOG_DBG("Fed the watchdog"); in mcux_wwdt_feed()
157 /* Watchdog is not running so does not need to be fed */ in wdt_rpi_pico_feed()
152 LOG_DBG("Fed the watchdog"); in mcux_wdog32_feed()
153 /* Watchdog is not running so does not need to be fed */ in wdt_nrf_feed()
217 * reloaded/fed with the 12-bit watchdog counter in wdt_sam_feed()
262 /* watchdog clock is fed by OSCULP32K */ in wdt_sam0_init()
146 fed to scanf and generate exactly the same binary value.
158 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
160 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
14 a different priority. The dispatch is handled by a MetaIRQ thread fed
158 /* Print a separator so the output can be fed into in log_backend_uart_init()
