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/Zephyr-latest/dts/bindings/display/panel/
Dpanel-timing.yaml120 0 drives pixel data on falling edge, and samples on rising edge.
121 1 drives pixel data on rising edge, and samples data on falling edge
129 Drive sync on rising or sample sync on falling edge. If not specified
131 Use 0 to drive sync on falling edge
134 and sample sync on falling edge of pixel clock.
/Zephyr-latest/dts/bindings/gpio/
Dzephyr,gpio-emul.yaml15 falling-edge:
16 description: Enables support for falling edge interrupt detection
/Zephyr-latest/dts/bindings/pinctrl/
Dnuvoton,npcx-pinctrl.yaml97 - "low-falling": Select the detection polarity to low/falling
100 - "low-falling"
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dgd32_exti.h24 /** Trigger on falling edge */
26 /** Trigger on rising and falling edge */
Dgpio_intc_stm32.h54 /* Trigger on falling edge */
56 /* Trigger on both rising and falling edge */
Dintc_xmc4xxx.h16 * @param trig Trigger edge type (falling, rising or both)
Dintc_eirq_nxp_s32.h24 /** Interrupt triggered on falling edge */
Dintc_wkpu_nxp_s32.h23 /** Interrupt triggered on falling edge */
/Zephyr-latest/dts/bindings/interrupt-controller/
Dst,stm32g0-exti.yaml8 dedicated Rising and Falling interrupt pending registers.
Dst,stm32h7rs-exti.yaml8 with two dedicated Rising and Falling interrupt pending registers
/Zephyr-latest/samples/drivers/charger/
DKconfig19 int "System voltage notification falling threshold in µV"
/Zephyr-latest/samples/subsys/tracing/
Dgpio.overlay12 falling-edge;
/Zephyr-latest/include/zephyr/drivers/sensor/
Dmcux_lpcmp.h36 /** LPCMP output falling event trigger. */
88 * 011b: COUT falling edge event close an active window
/Zephyr-latest/drivers/gpio/
Dgpio_pca953x.c48 uint8_t falling; member
122 if (!irq_state->rising && !irq_state->falling) { in gpio_pca953x_handle_interrupt()
138 /* Mask gpio transactions with rising/falling edge interrupt config */ in gpio_pca953x_handle_interrupt()
141 interrupt_status |= (irq_state->falling & transitioned_pins & in gpio_pca953x_handle_interrupt()
361 irq->falling &= ~BIT(pin); in gpio_pca953x_pin_interrupt_configure()
365 irq->falling |= BIT(pin); in gpio_pca953x_pin_interrupt_configure()
368 irq->falling |= BIT(pin); in gpio_pca953x_pin_interrupt_configure()
371 irq->falling &= ~BIT(pin); in gpio_pca953x_pin_interrupt_configure()
Dgpio_tca6424a.c31 uint32_t falling; member
193 if (!irq_state->rising && !irq_state->falling) { in tca6424a_handle_interrupt()
209 /* Mask gpio transactions with rising/falling edge interrupt config */ in tca6424a_handle_interrupt()
211 interrupt_status |= (irq_state->falling & transitioned_pins & previous_state); in tca6424a_handle_interrupt()
412 irq->falling &= ~BIT(pin); in tca6424a_pin_interrupt_configure()
416 irq->falling |= BIT(pin); in tca6424a_pin_interrupt_configure()
419 irq->falling |= BIT(pin); in tca6424a_pin_interrupt_configure()
422 irq->falling &= ~BIT(pin); in tca6424a_pin_interrupt_configure()
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dit8xxx2-wuc.h21 /** WUC falling edge trigger mode */
/Zephyr-latest/dts/bindings/misc/
Drenesas,ra-external-interrupt.yaml24 - "falling"
/Zephyr-latest/dts/bindings/watchdog/
Dti,tps382x.yaml17 when WDI sees a rising edge or a falling edge. If unused, the WDI
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml42 Set to indicate that the clock leading edge is falling (CPOL=1).
/Zephyr-latest/dts/bindings/stepper/adi/
Dadi,tmc2209.yaml42 This means that the step signal can be toggled on both the rising and falling edge.
/Zephyr-latest/subsys/net/lib/wifi_credentials/
DKconfig72 Wait period before falling back to the next entry in the list of stored SSIDs.
/Zephyr-latest/dts/bindings/video/
Dvideo-interfaces.yaml107 - 0 # falling
111 Sample data on falling, rising or both edges of the pixel clock signal.
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dpower.c67 * falling trip voltage, this is not impacting the voltage in anyway. in rt5xx_power_init()
/Zephyr-latest/drivers/adc/
Dadc_ads7052.c194 * A leading 0 is output on the SDO pin on the CS falling edge.
196 * after the first SCLK falling edge. Subsequent output bits are launched on the subsequent rising
200 * 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_qspi.h24 /* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */
26 /* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */
28 /* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */
30 /* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */

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