| /Zephyr-latest/dts/bindings/comparator/ |
| D | nxp,kinetis-acmp.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
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| /Zephyr-latest/dts/bindings/w1/ |
| D | adi,max32-w1.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32xxx MCUs 1-Wire Master
6 include: [w1-master.yaml, pinctrl-device.yaml]
8 compatible: "adi,max32-w1"
20 pinctrl-0:
23 pinctrl-names:
26 internal-pullup:
31 Set this field to enable the internal pullup resistor.
32 0 - Internal pullup disabled.
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | silabs,dbus-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8 pin. This pin controller is used for devices that use DBUS (Digital Bus)
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
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| D | nxp,lpc-iocon-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 LPC pinctrl node. This node defines pin configurations in pin groups, and has
7 pin configuration defines a peripheral's pin configuration. Each numbered
16 slew-rate = "standard";
22 IOCON_FUNC=<pin mux selection>,
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_gecko.c | 4 * SPDX-License-Identifier: Apache-2.0
41 #define GET_GECKO_GPIO_INDEX(id) (DT_INST_REG_ADDR(id) - DT_REG_ADDR(DT_NODELABEL(gpioa))) \
48 * See https://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf
53 * @param[in] pin The index of the pin. Valid values are 0..7.
57 #define GECKO_GPIO_MODEL(pin, mode) (mode << (pin * 4)) argument
61 * @param[in] pin The index of the pin. Valid values are 8..15.
65 #define GECKO_GPIO_MODEH(pin, mode) (mode << ((pin - 8) * 4)) argument
99 data->ports[data->count++] = dev; in gpio_gecko_add_port()
103 gpio_pin_t pin, in gpio_gecko_configure() argument
106 const struct gpio_gecko_config *config = dev->config; in gpio_gecko_configure()
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| D | gpio_andes_atcgpio100.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
29 #define REG_DOUT 0x24 /* Data Out reg. */
31 #define REG_DCLR 0x2C /* Data out clear reg. */
32 #define REG_DSET 0x30 /* Data out set reg. */
33 #define REG_PUEN 0x40 /* Pull enable reg. */
35 #define REG_INTE 0x50 /* Interrupt enable reg. */
41 #define REG_DEBE 0x70 /* De-bounce enable reg. */
42 #define REG_DEBC 0x74 /* De-Bounce control reg. */
56 ((const struct gpio_atcgpio100_config * const)(dev)->config)->base
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| D | gpio_adp5585.c | 4 * SPDX-License-Identifier: Apache-2.0
67 static int gpio_adp5585_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_adp5585_config() argument
69 const struct adp5585_gpio_config *cfg = dev->config; in gpio_adp5585_config()
70 struct adp5585_gpio_data *data = dev->data; in gpio_adp5585_config()
72 (struct mfd_adp5585_config *)(cfg->mfd_dev->config); in gpio_adp5585_config()
73 struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data); in gpio_adp5585_config()
78 /* ADP5585 has non-contiguous gpio pin layouts, account for this */ in gpio_adp5585_config()
79 if ((pin & cfg->common.port_pin_mask) == 0) { in gpio_adp5585_config()
80 LOG_ERR("pin %d is invalid for this device", pin); in gpio_adp5585_config()
81 return -ENOTSUP; in gpio_adp5585_config()
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| D | gpio_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
21 ((const struct gpio_b91_config *)dev->config)->gpio_base)
24 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
27 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
29 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
30 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
42 /* Max pin number per port (pin 0..7) */
45 /* IRQ Enable registers */
49 /* Pull-up/down resistors */
69 uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
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| D | gpio_npcx.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h>
50 ((struct gpio_reg *)((const struct gpio_npcx_config *)(dev)->config)->base)
62 void npcx_gpio_enable_io_pads(const struct device *dev, int pin) in npcx_gpio_enable_io_pads() argument
64 const struct gpio_npcx_config *const config = dev->config; in npcx_gpio_enable_io_pads()
65 const struct npcx_wui *io_wui = &config->wui_maps[pin]; in npcx_gpio_enable_io_pads()
67 if (io_wui->table == NPCX_MIWU_TABLE_NONE) { in npcx_gpio_enable_io_pads()
68 LOG_ERR("Cannot enable GPIO(%x, %d) pad", config->port, pin); in npcx_gpio_enable_io_pads()
73 * If this pin is configured as a GPIO interrupt source, do not in npcx_gpio_enable_io_pads()
76 if (pin < NPCX_GPIO_PORT_PIN_NUM && !npcx_miwu_irq_get_state(io_wui)) { in npcx_gpio_enable_io_pads()
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| D | gpio_sx1509b.c | 4 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
7 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/gpio/semtech-sx1509b.h>
119 /* Pin configuration register addresses */
153 * @brief Write a big-endian word to an internal address of an I2C slave.
160 * @retval -EIO General input / output error.
171 * @brief Write a big-endian byte to an internal address of an I2C slave.
178 * @retval -EIO General input / output error.
191 const struct sx1509b_config *cfg = dev->config; in sx1509b_handle_interrupt()
192 struct sx1509b_drv_data *drv_data = dev->data; in sx1509b_handle_interrupt()
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| D | gpio_kscan_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_port.h | 2 * Copyright (c) 2016-2017 Piotr Mienkowski
3 * Copyright (c) 2020-2022 Gerson Fernando Budke
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
17 * Pin flags/attributes
27 /* Open-Drain is a reserved entry at pinctrl driver */
29 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
32 /* Output-Enable, see dts/pinctrl/pincfg-node.yaml */
35 /* Drive-Strength, 0mA means normal, any other value means stronger */
38 /* Peripheral Multiplexer Enable */
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ams,tmd2620.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 int-gpios:
12 type: phandle-array
15 The interrupt pin of TMD2620 is open-drain, active low.
16 If connected directly the MCU, the pin should be configured
17 as pull-up, active low.
19 proximity-gain:
24 - 1
25 - 2
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| /Zephyr-latest/scripts/utils/ |
| D | pinctrl_nrf_migrate.py | 4 # SPDX-License-Identifier: Apache-2.0
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
31 [--header ""]
35 .. code-block:: devicetree
41 tx-pin = <5>;
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| /Zephyr-latest/include/zephyr/drivers/mfd/ |
| D | axp192.h | 4 * SPDX-License-Identifier: Apache-2.0
64 * @brief Request a GPIO pin to be configured to a specific function. GPIO0..5
74 * @retval -EINVAL if an invalid GPIO number is passed
75 * @retval -ENOTSUP if the requested function is not supported by the given
76 * @retval -errno in case of any bus error
82 * @brief Read out current configuration of a specific GPIO pin.
88 * @retval -EINVAL if an invalid GPIO number is passed
89 * @retval -errno in case of any bus error
94 * @brief Enable pull-down on specified GPIO pin. AXP192 only supports
95 * pull-down on GPIO3..5. Pull-ups are not supported.
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| D | mfd_ite_it8801.h | 4 * SPDX-License-Identifier: Apache-2.0
20 /* 0xfb: Gather interrupt enable control register */
63 /* GPIO pull-down enable */
65 /* GPIO pull-up enable */
71 /* 0x40: Keyboard scan out mode control register */
80 /* Control push-pull flag */
82 /* 0x5f: PWM output open-drain disable register */
100 #define IT8801_DEV_MFD_PIN(idx, inst) DT_PHA(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls, pin)
106 .pin = IT8801_DEV_MFD_PIN(idx, inst), \
116 * Configure alternate function pin
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| /Zephyr-latest/soc/silabs/silabs_sim3/sim3u/ |
| D | gen_crossbar_config.py | 5 # SPDX-License-Identifier: Apache-2.0
9 The SiM3U1xx SoCs do support pinmuxing, but with many limimitations. It's also non-optional, so we
18 - crossbar 0: Controls portbanks 0 and 1
19 - crossbar 1: Controls portbanks 2 and 3
21 Each crossbar has two configuration-values which reside in different registers:
22 - config: A bitmask which tells the crossbar which peripherals should be muxed. Some peripherals
24 - enable: A bit which enables or disables the whole crossbar. When disabled, all pins of the
28 - pbskipen: A bitmask where value `1` means, that the pin will not be muxed.
29 The index of the bit refers to the pin number.
34 available pin. That has a few implications:
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | s32z2xxdc2_s32z270_rtu0.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
10 /* Pin 1 and 3 of J69 must be connected on the board */
12 compatible = "test-gpio-basic-api";
13 out-gpios = <&gpioa 11 0>;
14 in-gpios = <&gpioa 12 0>;
22 input-enable;
28 pinctrl-0 = <&eirq0_default>;
29 pinctrl-names = "default";
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| D | s32z2xxdc2_s32z270_rtu1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
10 /* Pin 1 and 3 of J69 must be connected on the board */
12 compatible = "test-gpio-basic-api";
13 out-gpios = <&gpioa 11 0>;
14 in-gpios = <&gpioa 12 0>;
22 input-enable;
28 pinctrl-0 = <&eirq0_default>;
29 pinctrl-names = "default";
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_mci_io_mux.c | 4 * SPDX-License-Identifier: Apache-2.0
20 * these mux options are needed to clear pin mux settings to
26 * Helper function to handle setting pin properties,
27 * such as pin bias and slew rate
32 volatile uint32_t *pull_reg = &soc_ctrl->PAD_PU_PD_EN0; in configure_pin_props()
33 volatile uint32_t *slew_reg = &soc_ctrl->SR_CONFIG0; in configure_pin_props()
34 volatile uint32_t *sleep_force_en = &soc_ctrl->PAD_SLP_EN0; in configure_pin_props()
35 volatile uint32_t *sleep_force_val = &soc_ctrl->PAD_SLP_VAL0; in configure_pin_props()
37 /* GPIO 22-27 use always on configuration registers */ in configure_pin_props()
39 pull_reg = (&aon_soc_ciu->PAD_PU_PD_EN1 - 1); in configure_pin_props()
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| /Zephyr-latest/modules/nrf_wifi/bus/ |
| D | rpu_hw_if.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
76 return -1; in validate_addr_blk()
85 end_addr = start_addr + len - 1; in rpu_validate_addr()
97 LOG_ERR("Address validation failed - pls check memmory map and re-try"); in rpu_validate_addr()
98 return -1; in rpu_validate_addr()
103 return -1; in rpu_validate_addr()
106 cfg->qspi_slave_latency = (*hl_flag) ? rpu_7002_memmap[selected_blk][2] : 0; in rpu_validate_addr()
116 LOG_ERR("Host IRQ GPIO %s is not ready", host_irq_spec.port->name); in rpu_irq_config()
117 return -ENODEV; in rpu_irq_config()
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| /Zephyr-latest/samples/boards/nordic/nrfx/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
28 static void button_handler(nrfx_gpiote_pin_t pin, in button_handler() argument
69 /* Initialize input pin to generate event on high to low transition in main()
93 /* Initialize output pin. SET task will turn the LED on, in main()
94 * CLR will turn it off and OUT will toggle it. in main()
126 /* Configure endpoints of the channel so that the input pin event is in main()
127 * connected with the output pin OUT task. This means that each time in main()
128 * the button is pressed, the LED pin will be toggled. in main()
134 /* Enable the channel. */ in main()
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| /Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/src/ |
| D | test_pin_interrupt.c | 4 * SPDX-License-Identifier: Apache-2.0
20 "Detected interrupt on an invalid pin"); in callback_edge()
31 "Detected interrupt on an invalid pin"); in callback_level()
37 "Failed to disable pin interrupt in the callback"); in callback_level()
41 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
45 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
46 "Test point %d: failed to set logical pin value", idx); in pin_set_and_verify()
61 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in test_gpio_pin_interrupt_edge()
64 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_edge()
65 TC_PRINT("Simultaneous pin in/out mode is not supported.\n"); in test_gpio_pin_interrupt_edge()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_nxp_flexio.c | 4 * SPDX-License-Identifier: Apache-2.0
58 /** Timer Pin output disabled */
60 /** Timer Pin Output mode */
65 /** Flexio used pin index */
97 const struct pwm_nxp_flexio_config *config = dev->config; in pwm_nxp_flexio_set_cycles()
98 struct pwm_nxp_flexio_data *data = dev->data; in pwm_nxp_flexio_set_cycles()
101 FLEXIO_Type *flexio_base = (FLEXIO_Type *)(config->flexio_base); in pwm_nxp_flexio_set_cycles()
102 struct nxp_flexio_child *child = (struct nxp_flexio_child *)(config->child); in pwm_nxp_flexio_set_cycles()
106 if (channel >= config->pulse_info->pwm_pulse_channels) { in pwm_nxp_flexio_set_cycles()
108 return -EINVAL; in pwm_nxp_flexio_set_cycles()
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| /Zephyr-latest/boards/nxp/mr_canhubk3/ |
| D | mr_canhubk3.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
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