Home
last modified time | relevance | path

Searched +full:enable +full:- +full:high +full:- +full:speed +full:- +full:mode (Results 1 – 25 of 121) sorted by relevance

12345

/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
[all …]
/Zephyr-latest/tests/drivers/build_all/comparator/mcux_acmp/
Dmimxrt1176_mux_dac.dts4 * SPDX-License-Identifier: Apache-2.0
11 drive-strength = "high";
12 bias-pull-up;
13 slew-rate = "fast";
20 pinctrl-0 = <&acmp1_default>;
21 pinctrl-names = "default";
23 positive-mux-input = "IN2";
24 positive-port-input = "MUX";
25 negative-mux-input = "IN2";
26 negative-port-input = "DAC";
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,numaker-scc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nuvoton,numaker-scc"
8 include: [clock-controller.yaml, base.yaml]
17 Enable/disable 4~24 MHz external crystal oscillator (HXT)
19 - "untouched"
20 - "enable"
21 - "disable"
26 Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT)
28 - "untouched"
29 - "enable"
[all …]
/Zephyr-latest/dts/bindings/mipi-dsi/
Dnxp,mipi-dsi-2l.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mipi-dsi-2l"
10 include: mipi-dsi-host.yaml
20 in video mode
21 dpi-color-coding:
24 - "16-bit-config-1"
25 - "16-bit-config-2"
26 - "16-bit-config-3"
27 - "18-bit-config-1"
28 - "18-bit-config-2"
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
[all …]
/Zephyr-latest/drivers/i2c/
DKconfig.sam02 # SPDX-License-Identifier: Apache-2.0
10 Enable the SAM0 series SERCOM I2C driver.
18 DMA driven mode requires fewer interrupts to handle the
19 transaction and ensures that high speed modes are not delayed
Di2c_sam_twihs.c5 * SPDX-License-Identifier: Apache-2.0
13 * Only I2C Master Mode with 7 bit addressing is currently supported.
32 #include "i2c-priv.h"
34 /** I2C bus speed [Hz] in Standard Mode */
36 /** I2C bus speed [Hz] in Fast Mode */
38 /** I2C bus speed [Hz] in High Speed Mode */
72 static int i2c_clk_set(Twihs *const twihs, uint32_t speed) in i2c_clk_set() argument
82 cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3) in i2c_clk_set()
94 return -EIO; in i2c_clk_set()
98 twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div) in i2c_clk_set()
[all …]
Di2c_sam_twihs_rtio.c6 * SPDX-License-Identifier: Apache-2.0
14 * Only I2C Controller Mode with 7 bit addressing is currently supported.
33 #include "i2c-priv.h"
35 /** I2C bus speed [Hz] in Standard Mode */
37 /** I2C bus speed [Hz] in Fast Mode */
39 /** I2C bus speed [Hz] in High Speed Mode */
60 static int i2c_clk_set(Twihs *const twihs, uint32_t speed) in i2c_clk_set() argument
70 cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3) in i2c_clk_set()
82 return -EIO; in i2c_clk_set()
86 twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div) in i2c_clk_set()
[all …]
Di2c_sam4l_twim.c3 * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
13 * I2C Master Mode with 7/10 bit addressing is currently supported.
33 #include "i2c-priv.h"
35 /** I2C bus speed [Hz] in Standard Mode */
37 /** I2C bus speed [Hz] in Fast Mode */
39 /** I2C bus speed [Hz] in Fast Plus Mode */
41 /** I2C bus speed [Hz] in High Speed Mode */
52 /** Interrupt Enable Register Mask for No Acknowledgements */
54 /** Frequently used Interrupt Enable Register Mask */
[all …]
Di2c_ite_enhance.c4 * SPDX-License-Identifier: Apache-2.0
23 #include "i2c-priv.h"
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
110 /* Target mode DMA output buffer. */
113 /* Target mode DMA input buffer. */
139 /* Store command queue mode messages. */
174 /* Mode select */
176 /* I2C interrupt enable */
178 /* 0 : Standard mode , 1 : Receive mode */
186 /* Start with command queue mode */
[all …]
Di2c_npcx_controller.c4 * SPDX-License-Identifier: Apache-2.0
15 * support for a two-wire SMBus/I2C synchronous serial interface. The following
21 * +<----------------+<----------------------+
23 * +------+ +------------+ | +------- ----+ | +------- -------+ |
24 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
25 * | +------+ +------------+ +------------+ Yes +---------------+ |
27 * | +-----------+ |
28 * +--------------------------------------------| WAIT_STOP |<------------+
29 * STOP is completed +-----------+ Issue STOP
35 * +<-----------------+<---------------------+
[all …]
Di2c_dw.c1 /* dw_i2c.c - I2C file for Design Ware */
5 * Copyright (c) 2022 Andrei-Edward Popa
7 * SPDX-License-Identifier: Apache-2.0
49 #include "i2c-priv.h"
57 void i2c_dw_enable_idma(const struct device *dev, bool enable) in i2c_dw_enable_idma() argument
62 if (enable) { in i2c_dw_enable_idma()
76 const struct i2c_dw_rom_config *const rom = dev->config; in cb_i2c_idma_transfer()
77 struct i2c_dw_dev_config *const dw = dev->data; in cb_i2c_idma_transfer()
79 dma_stop(rom->dma_dev, channel); in cb_i2c_idma_transfer()
83 dw->xfr_status = true; in cb_i2c_idma_transfer()
[all …]
/Zephyr-latest/drivers/ethernet/
DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
19 Enable STM32 HAL based Ethernet driver. It is available for
57 especially under high load.
84 PHY's carrier status is re-evaluated.
87 bool "Autonegotiation mode"
90 Enable this if using autonegotiation
96 Enable receive and transmit checksum offload to enhance throughput
103 bool "Set speed to 10 Mbps when autonegotiation is disabled"
105 Set this if using 10 Mbps and when autonegotiation is disabled, otherwise speed
109 bool "Half duplex mode"
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpower.c4 * SPDX-License-Identifier: Apache-2.0
7 * sleep mode must be defined within this file, or linked to RAM.
28 * normal/full speed mode, low speed mode, and low power mode.
35 __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); in imxrt_clock_pm_callbacks_register()
36 lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; in imxrt_clock_pm_callbacks_register()
37 lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; in imxrt_clock_pm_callbacks_register()
38 if (callbacks->clock_lpm_init) { in imxrt_clock_pm_callbacks_register()
39 lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; in imxrt_clock_pm_callbacks_register()
43 static void lpm_set_sleep_mode_config(clock_mode_t mode) in lpm_set_sleep_mode_config() argument
50 * ERR050143: CCM: When improper low-power sequence is used, in lpm_set_sleep_mode_config()
[all …]
/Zephyr-latest/include/zephyr/drivers/usb/
Dudc.h2 * Copyright (c) 2021-2022 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
37 /** USB high speed capable controller */
52 * @brief USB device actual speed
57 /** Device is connected to a full speed bus */
59 /** Device is connected to a high speed bus */
61 /** Device is connected to a super speed bus */
79 /** High-Bandwidth (interrupt or iso) capable endpoint */
147 * Non-correctable error event, requires attention from higher
247 const uint8_t mode, const bool dryrun);
[all …]
/Zephyr-latest/include/zephyr/sd/
Dsd_spec.h2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
25 * specific to SDIO cards, or cards running in SPI mode instead of native SD
26 * mode.
61 SD_SPI_READ_OCR = 58, /* SPI mode only */
62 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */
69 * to inform the SD card the next command is an application-specific one.
82 * @brief Native SD mode R1 response status flags
87 /* Bits 0-2 reserved */
99 /* Bits 17-18 reserved */
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c4 * SPDX-License-Identifier: Apache-2.0
38 #define RCAR_PWM_CR_CCMD BIT(15) /* Frequency Division Mode */
41 #define RCAR_PWM_CR_EN BIT(0) /* Channel Enable */
50 #define RCAR_PWM_CNT_PH_MASK 0x000003ff /* PWM High-Level Period */
67 return sys_read32(config->reg_addr + offs); in pwm_rcar_read()
72 sys_write32(value, config->reg_addr + offs); in pwm_rcar_write()
102 /* Reducing clock speed */ in pwm_rcar_update_clk()
109 return -ENOTSUP; in pwm_rcar_update_clk()
113 /* Increasing clock speed */ in pwm_rcar_update_clk()
116 return -ENOTSUP; in pwm_rcar_update_clk()
[all …]
/Zephyr-latest/boards/nxp/ls1046ardb/doc/
Dindex.rst6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
[all …]
/Zephyr-latest/drivers/wifi/esp32/
DKconfig.esp3217 Enable ESP32 SoC WiFi support. Only supported in single
18 core mode because the network stack is not aware of SMP
27 Make sure there is a minimal heap available for Wi-Fi driver.
46 bool "Activates the Station/AP co-existence mode."
49 The Station/AP coexistence mode allows the ESP32 to operate as both a station and
50 an access point simultaneously. This mode is not enabled by default.
93 and then delivers it to the high layer TCP/IP stack. The dynamic RX buffer
108 initialized and released when WiFi is de-initialized. The size of each
185 when WiFi is de-initialized. The size of each static RX MGMT buffer is fixed to about 500 Bytes.
215 Select this option to enable CSI(Channel State Information) feature.
[all …]
/Zephyr-latest/boards/st/steval_stwinbx1/doc/
Dindex.rst6 The STWIN.box (STEVAL-STWINBX1) is a development kit that features an Arm|reg| Cortex|reg|-M33 base…
10 The STEVAL-STWINBX1 kit consists of an STWIN.box core system, a 480mAh LiPo battery, an adapter for…
13 More information about the board can be found at the `STEVAL-STWINBX1 Development kit website`_.
19 The STEVAL-STWINBX1 provides motion, environmental, and audio
20 sensor data through either the built-in RS485 transceiver, BLE, Wi-Fi, and
23 - Multisensing wireless platform for vibration monitoring and ultrasound detection
24 - Baby crying detection with Cloud AI learning
25 - Barometer / environmental monitoring
26 - Vehicle / goods tracking
27 - Vibration monitoring
[all …]
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h3 * SPDX-License-Identifier: Apache-2.0
26 /* SRS09 - Present State Register */
30 /* SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up) */
64 * • 1111b - Reserved
65 * • 1110b - t_sdmclk*2(27+2)
66 * • 1101b - t_sdmclk*2(26+2)
100 /* V18SE is 0 for DS and HS, 1 for UHS-I */
217 /* Auto CMD Enable */
227 /* HRS07 - IO Delay Information Register */
232 /* HRS09 - PHY Control and Status Register */
[all …]
/Zephyr-latest/boards/arduino/portenta_h7/
Darduino_portenta_h7-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "gpio-leds";
24 compatible = "usb-ulpi-phy";
25 reset-gpios = < &gpioj 4 GPIO_ACTIVE_LOW >;
26 #phy-cells = <0>;
52 pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pi9>;
53 pinctrl-names = "default";
54 current-speed = <115200>;
59 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
60 pinctrl-names = "default";
[all …]
/Zephyr-latest/include/zephyr/net/
Dmdio.h4 * SPDX-License-Identifier: Apache-2.0
42 /** IEEE 802.3 45.3.4 post-read-increment-address operation */
62 /** Auto-negotiation */
88 /** Speed ability */
104 /* Auto-negotiation Register: EEE advertisement Register */
108 /* BASE-T1 registers */
109 /** BASE-T1 Auto-negotiation control */
111 /** BASE-T1 Auto-negotiation status */
113 /** BASE-T1 Auto-negotiation advertisement register [15:0] */
115 /** BASE-T1 Auto-negotiation advertisement register [31:16] */
[all …]
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst6 STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz
10 module on other boards as HCI layer (Specefically B-U585I-IOT02A Development board).
14 - Bluetooth module in SiP-LGA86 package
15 - Integrated chip antenna
16 - Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0, OpenThread certified
18 - IEEE 802.15.4-2011 MAC PHY Supports 2 Mbits/s
19 - Frequency band 2402-2480 MHz
20 - Advertising extension
21 - Tx output power up to +6 dBm
22 - Rx sensitivity: -96 dBm (Bluetooth|reg| Low Energy at 1 Mbps), -100 dBm (802.15.4)
[all …]
/Zephyr-latest/boards/m5stack/m5stack_core2/
Dm5stack_core2_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "m5stack_core2-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/display/ili9xxx.h>
13 #include <zephyr/dt-bindings/regulator/axp192.h>
21 pwr-led = &pwr_led;
22 uart-0 = &uart0;
23 i2c-0 = &i2c0;
33 zephyr,shell-uart = &uart0;
36 zephyr,code-partition = &slot0_partition;
[all …]

12345