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/Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/boards/
Dxmc47_relax_kit.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This sample requires several connections listed below. However, no external pull-ups
14 #include <zephyr/dt-bindings/i2c/i2c.h>
17 compatible = "infineon,xmc4xxx-i2c";
21 /delete-property/ miso-src;
23 clock-frequency = <I2C_BITRATE_STANDARD>;
24 pinctrl-0 = <&i2c_scl_p5_2_u2c0 &i2c_sda_dx0_p3_7_u2c0 &i2c_sda_dout0_p3_8_u2c0>;
25 pinctrl-names = "default";
27 scl-src = "DX1A";
28 sda-src = "DX0C";
[all …]
/Zephyr-Core-3.5.0/boards/arm/apollo4p_evb/
Dapollo4p_evb-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
[all …]
/Zephyr-Core-3.5.0/boards/arm/apollo4p_blue_kxr_evb/
Dapollo4p_blue_kxr_evb-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dti,cc13xx-cc26xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
29 - drive-strength: Minimum current that can be sourced from the pin.
30 - input-enable: enable input.
31 - input-schmitt-enable: enable input schmitt circuit.
32 - ti,input-edge-detect: enable and configure edge detection interrupts
[all …]
Dmicrochip,xec-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
[all …]
Dti,cc32xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
57 - drive-open-drain: Open-drain drive mode.
[all …]
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
37 description: enable pull-down resistor
[all …]
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
17 slew-rate = "normal";
18 drive-strength = "normal";
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
40 compatible: "nxp,rt-iocon-pinctrl"
[all …]
Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
21 Both pins will be configured with a slow slew rate, and minimum drive
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
28 bias-pull-down: PUE=0, PE=1
29 drive-open-drain: ODE=1
30 slew-rate: FSEL=<enum_idx>
[all …]
Dnxp,mcux-rt11xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "high";
16 slew-rate = "slow";
20 Both pins will be configured with a weak latch, high drive strength,
25 drive-open-drain: ODE/ODE_LPSR=1
26 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27 bias-pull-down: PUE=1, PUS=0
28 bias-pull-up: PUE=1, PUS=1
29 bias-disable: PULL=11 (in supported registers)
30 slew-rate: SRE=<enum_idx>
[all …]
/Zephyr-Core-3.5.0/dts/riscv/ite/
Dit8xxx2-pinctrl-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
115 bias-pull-up;
119 bias-pull-up;
123 bias-pull-up;
127 bias-pull-up;
131 bias-pull-up;
135 bias-pull-up;
139 bias-pull-up;
143 bias-pull-up;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/i2c/
Dinfineon,xmc4xxx-i2c.yaml4 # SPDX-License-Identifier: Apache-2.0
16 compatible = "infineon,xmc4xxx-i2c";
19 pinctrl-0 = <&i2c_scl_p0_13_u1c1 &i2c_sda_p3_15_u1c1>;
20 pinctrl-names = "default";
21 scl-src = "DX1B";
22 sda-src = "DX0A";
25 #address-cells = <1>;
26 #size-cells = <0>;
28 clock-frequency = <I2C_BITRATE_STANDARD>;
35 The pinctrl nodes need to be configured as open-drain and
[all …]
/Zephyr-Core-3.5.0/tests/drivers/w1/w1_api/boards/
Dnucleo_g0b1re.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * enable open-drain drive such that no external push-pull to
10 * open-drain converter is required. An external pull-up resistor
14 drive-open-drain;
15 bias-pull-up;
/Zephyr-Core-3.5.0/boards/arm/mec1501modular_assy6885/
Dmec1501modular_assy6885-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <microchip/mec152x/mec152xhsz-pinctrl.dtsi>
13 drive-open-drain;
17 drive-open-drain;
21 drive-open-drain;
25 drive-open-drain;
29 bias-pull-up;
33 bias-pull-up;
37 bias-pull-up;
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec15xxevb_assy6853/
Dmec15xxevb_assy6853-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <microchip/mec152x/mec152xhsz-pinctrl.dtsi>
13 drive-open-drain;
17 drive-open-drain;
21 drive-open-drain;
25 drive-open-drain;
29 bias-pull-up;
33 bias-pull-up;
37 bias-pull-up;
[all …]
/Zephyr-Core-3.5.0/boards/arm/xmc47_relax_kit/
Dxmc47_relax_kit-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <infineon/xmc4700_F144x2048-pinctrl.dtsi>
9 drive-strength = "strong-soft-edge";
10 drive-push-pull;
15 drive-strength = "strong-soft-edge";
20 drive-strength = "strong-soft-edge";
21 drive-push-pull;
26 drive-strength = "strong-soft-edge";
31 drive-strength = "strong-soft-edge";
32 drive-push-pull;
[all …]
/Zephyr-Core-3.5.0/boards/arm/hexiwear_k64/
Dhexiwear_k64-pinctrl.dtsi6 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/kinetis/MK64FN1M0VDC12-pinctrl.h>
17 drive-strength = "low";
18 slew-rate = "fast";
26 drive-strength = "low";
27 drive-open-drain;
28 slew-rate = "fast";
36 drive-strength = "low";
37 drive-open-drain;
38 slew-rate = "fast";
[all …]
/Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_api/boards/
Dxmc47_relax_kit.overlay5 * SPDX-License-Identifier: Apache-2.0
10 i2c-0 = &usic0ch1;
15 drive-strength = "strong-sharp-edge";
16 drive-open-drain;
21 drive-strength = "strong-soft-edge";
22 drive-open-drain;
27 compatible = "infineon,xmc4xxx-i2c";
28 pinctrl-0 = <&i2c_scl_p6_2_u0c1 &i2c_sda_p3_13_u0c1>;
29 pinctrl-names = "default";
30 scl-src = "DX1C";
[all …]
Dcy8cproto_063_ble.overlay2 * SPDX-License-Identifier: Apache-2.0
11 i2c-0 =&i2c1;
16 compatible = "infineon,cat1-i2c";
19 pinctrl-0 = <&p10_0_scb1_i2c_scl &p10_1_scb1_i2c_sda>;
20 pinctrl-names = "default";
25 drive-open-drain;
26 input-enable;
30 drive-open-drain;
31 input-enable;
/Zephyr-Core-3.5.0/boards/arm/mec172xmodular_assy6930/
Dmec172xmodular_assy6930.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
28 pwm-0 = &pwm0;
32 compatible = "gpio-leds";
49 clock-frequency = <96000000>;
77 current-speed = <115200>;
78 pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
79 pinctrl-names = "default";
84 pinctrl-0 = <&adc00_gpio200 &adc03_gpio203
[all …]
/Zephyr-Core-3.5.0/boards/arm/frdm_k82f/
Dfrdm_k82f-pinctrl.dtsi6 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/kinetis/MK82FN256VLL15-pinctrl.h>
16 drive-strength = "low";
17 slew-rate = "fast";
26 drive-strength = "low";
27 slew-rate = "fast";
35 drive-strength = "low";
36 drive-open-drain;
37 slew-rate = "fast";
45 drive-strength = "low";
[all …]
/Zephyr-Core-3.5.0/boards/arm/rddrone_fmuk66/
Drddrone_fmuk66-pinctrl.dtsi6 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/kinetis/MK66FN2M0VMD18-pinctrl.h>
16 drive-strength = "low";
17 drive-open-drain;
18 bias-pull-up;
19 slew-rate = "fast";
30 drive-strength = "low";
31 slew-rate = "fast";
39 drive-strength = "low";
40 slew-rate = "fast";
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec172xevb_assy6906/
Dmec172xevb_assy6906.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
26 i2c-0 = &i2c_smb_0;
29 pwm-0 = &pwm0;
34 compatible = "gpio-leds";
53 clock-frequency = <96000000>;
81 current-speed = <115200>;
82 pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
83 pinctrl-names = "default";
[all …]
/Zephyr-Core-3.5.0/boards/arm/vmu_rt1170/
Dvmu_rt1170-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1176dvmaa-pinctrl.dtsi>
17 drive-strength = "high";
18 bias-pull-down;
19 slew-rate = "fast";
24 drive-strength = "high";
25 bias-pull-down;
26 slew-rate = "fast";
27 input-enable;
35 drive-strength = "high";
[all …]
/Zephyr-Core-3.5.0/boards/arm/cc1352r1_launchxl/
Dcc1352r1_launchxl-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h>
13 bias-disable;
17 bias-disable;
18 input-enable;
24 bias-pull-up;
25 drive-open-drain;
26 input-enable;
30 bias-pull-up;
31 drive-open-drain;
[all …]

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