1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10  for example, here is an group configuring LPUART1 pins:
11
12  group0 {
13    pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx:,
14      &iomuxc_uart4_txd_uart_tx_uart4_tx>;
15      bias-pull-up;
16      slew-rate = "slow";
17      drive-strength = "x1";
18  };
19
20  This will select UART4_RXD as UART4 rx, and UART4_TXD as UART4 tx.
21  Both pins will be configured with a slow slew rate, and minimum drive
22  strength.
23  Note that the soc level iomuxc dts file can be examined to find the possible
24  pinmux options. Here are the affects of each property on the
25  IOMUXC SW_PAD_CTL register:
26  input-schmitt-enable: HYS=1
27  bias-pull-up: PUE=1, PE=1
28  bias-pull-down: PUE=0, PE=1
29  drive-open-drain: ODE=1
30  slew-rate: FSEL=<enum_idx>
31  drive-strength: DSE=<enum_idx>
32  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
33
34  If only required properties are supplied, the pin will have the following
35  configuration:
36  HYS=0,
37  PE=0
38  PUE=0
39  ODE=0,
40  SRE=<slew-rate>,
41  DSE=<drive-strength>,
42  SION=0,
43
44
45compatible: "nxp,imx8mp-pinctrl"
46
47include: base.yaml
48
49child-binding:
50  description: iMX pin controller pin group
51  child-binding:
52    description: |
53      iMX pin controller pin configuration node.
54
55    include:
56      - name: pincfg-node.yaml
57        property-allowlist:
58          - input-schmitt-enable
59          - drive-open-drain
60          - input-enable
61          - bias-pull-up
62          - bias-pull-down
63
64    properties:
65      pinmux:
66        required: true
67        type: phandles
68        description: |
69          Pin mux selections for this group. See the soc level iomuxc DTSI file
70          for a defined list of these options.
71      drive-strength:
72        required: true
73        type: string
74        enum:
75          - "x1"
76          - "x4"
77          - "x2"
78          - "x6"
79        description: |
80          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
81          00 X1- low drive strength
82          01 X4- high drive strength
83          10 X2- medium drive strength
84          11 X6- max drive strength
85      slew-rate:
86        required: true
87        type: string
88        enum:
89          - "slow"
90          - "fast"
91        description: |
92          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
93          0 SLOW — Slow Frequency Slew Rate
94          1 FAST — Fast Frequency Slew Rate
95