| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | Kconfig | 1 # DMA configuration options
7 # DMA options
9 menuconfig DMA config
10 bool "Direct Memory Access (DMA) drivers"
12 if DMA
14 bool "DMA 64 bit address support"
17 DMA addresses are supported.
20 int "DMA init priority"
23 DMA driver device initialization priority.
25 module = DMA
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| D | Kconfig.iproc_pax | 6 prompt "Broadcom PAX(PCIE<->AXI) DMA driver"
13 prompt "Broadcom PAX(PCIE<->AXI) DMA driver version 2"
28 bool "PAX DMA paranoid debug checks"
31 alignments for each dma packet.
34 prompt "PAX DMA API modes"
38 bool "PAX DMA API in polling mode"
40 PAX DMA API polls for dma completions
43 bool "PAX DMA synchronous API with interrupt support"
45 PAX DMA API blocks until dma completion alert is
51 prompt "PAX DMA Ring operation mode"
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| D | Kconfig.stm32 | 1 # DMA configuration options
9 bool "STM32 DMA driver"
17 Driver for STM32 DMA V1, V2, V2bis and BDMA types.
20 bool "STM32U5 serie DMA driver"
25 Enable DMA support mainly for stm32U5 family.
26 It differs from the DMA driver due to the GPDMA peripheral.
35 Enable DMA V1 support.
42 Enable DMA V2 or DMA V2bis support. With the versions V2 of DMA, the
43 peripheral request must be specified in the dma slot of the dma cell
44 With the versions V2 bis of DMA, the peripheral request (slot) is not
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| D | dma_stm32u5.c | 10 * @brief Common part of DMA drivers for stm32U5.
19 #include <zephyr/drivers/dma/dma_stm32.h>
49 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq() local
51 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
57 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq() local
59 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
60 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
61 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
102 static inline bool dma_stm32_is_dte_active(DMA_TypeDef *dma, uint32_t id) in dma_stm32_is_dte_active() argument
104 return LL_DMA_IsActiveFlag_DTE(dma, dma_stm32_id_to_stream(id)); in dma_stm32_is_dte_active()
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| D | dma_stm32_v1.c | 8 * @brief DMA low level driver implementation for F2/F4/F7 series SoCs.
17 /* DMA burst length */
238 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id) in stm32_dma_dump_stream_irq() argument
241 dma_stm32_is_tc_active(dma, id), in stm32_dma_dump_stream_irq()
242 dma_stm32_is_ht_active(dma, id), in stm32_dma_dump_stream_irq()
243 dma_stm32_is_te_active(dma, id), in stm32_dma_dump_stream_irq()
244 dma_stm32_is_dme_active(dma, id), in stm32_dma_dump_stream_irq()
245 dma_stm32_is_fe_active(dma, id)); in stm32_dma_dump_stream_irq()
248 inline bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_tc_irq_active() argument
250 return LL_DMA_IsEnabledIT_TC(dma, dma_stm32_id_to_stream(id)) && in stm32_dma_is_tc_irq_active()
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| D | Kconfig.intel_adsp_hda | 7 bool "Intel ADSP HDA Host In DMA drivers"
10 depends on DMA
13 Intel ADSP Host HDA DMA driver.
16 bool "Intel ADSP HDA Host Out DMA drivers"
21 Intel ADSP Host HDA DMA driver.
24 bool "Intel ADSP HDA Link In DMA drivers"
29 Intel ADSP Link In HDA DMA driver.
32 bool "Intel ADSP HDA Link Out DMA drivers"
37 Intel ADSP Link Out HDA DMA driver.
43 Intel ADSP HDA DMA driver.
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| D | dma_xmc4xxx.c | 13 #include <zephyr/drivers/dma.h>
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
41 XMC_DMA_t *dma; member
53 uint32_t channels_event = get_channels_event(dma); \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
75 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_isr() local
79 /* There are two types of possible DMA error events: */ in dma_xmc4xxx_isr()
80 /* 1. Error response from AHB slave on the HRESP bus during DMA transfer. */ in dma_xmc4xxx_isr()
85 event = XMC_DMA_GetEventStatus(dma); in dma_xmc4xxx_isr()
126 XMC_DMA_t *dma = dev_cfg->dma; in dma_xmc4xxx_config() local
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| D | dma_stm32_v2.c | 8 * @brief DMA low level driver implementation for F0/F1/F3/L0/L4 series SoCs.
253 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id) in stm32_dma_dump_stream_irq() argument
256 dma_stm32_is_tc_active(dma, id), in stm32_dma_dump_stream_irq()
257 dma_stm32_is_ht_active(dma, id), in stm32_dma_dump_stream_irq()
258 dma_stm32_is_te_active(dma, id), in stm32_dma_dump_stream_irq()
259 dma_stm32_is_gi_active(dma, id)); in stm32_dma_dump_stream_irq()
262 bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_tc_irq_active() argument
264 return LL_DMA_IsEnabledIT_TC(dma, dma_stm32_id_to_stream(id)) && in stm32_dma_is_tc_irq_active()
265 dma_stm32_is_tc_active(dma, id); in stm32_dma_is_tc_irq_active()
268 bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id) in stm32_dma_is_ht_irq_active() argument
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| /Zephyr-Core-3.5.0/dts/xtensa/intel/ |
| D | intel_adsp_cavs.dtsi | 11 lpgpdma0: dma@7c000 {
13 #dma-cells = <1>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
24 lpgpdma1: dma@7d000 {
26 #dma-cells = <1>;
31 dma-buf-size-alignment = <4>;
32 dma-copy-alignment = <4>;
37 hda_link_out: dma@72400 {
39 #dma-cells = <1>;
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | nxp,lpc-dma.yaml | 4 description: NXP LPC DMA controller
6 compatible: "nxp,lpc-dma"
8 include: dma-controller.yaml
17 dma-channels:
20 nxp,dma-num-of-otrigs:
22 description: Number of Inputmux connections a DMA channel can receive from
24 nxp,dma-otrig-base-address:
26 description: Address used when listening to Inputmux DMA signals
28 nxp,dma-itrig-base-address:
30 description: DMA Channel Selection Address used for receiving signals
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| D | st,stm32-dma-v2.yaml | 5 STM32 DMA controller (V2)
8 This DMA controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. channel: the dma stream from 1 to <dma-requests>
16 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
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| D | st,stm32-dma.yaml | 5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
9 Each stm32 soc with a DMA is of a special version type, which could be
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
33 for 1st dma instance, offset is 0,
34 for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
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| D | dma-controller.yaml | 4 # Common fields for DMA controllers
8 bus: dma
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier
16 dma-channel-mask:
19 Bitmask of available DMA channels in ascending order that are
23 dma-channels:
25 description: Number of DMA channels supported by the controller
27 dma-requests:
29 description: Number of DMA request signals supported by the controller.
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| D | st,stm32-dma-v1.yaml | 5 STM32 DMA controller (V1)
8 This DMA controller includes FIFO control registers.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
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| D | st,stm32-dma-v2bis.yaml | 5 STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
7 This DMA controller includes several channels with different requests.
8 All the requests ar ORed before entering the DMA, so that only one request
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
15 A name custom DMA flags for channel configuration is used
17 -bit 5 : DMA cyclic mode config
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| D | arm,dma-pl330.yaml | 5 PL330 DMA Controller
7 A phandle to the DMA controller plus "channel" integer cell specifying
10 Example for pl330 DMA Controller
12 compatible = "arm,dma-pl330";
14 dma-channels = <8>;
15 #dma-cells = <1>;
18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
23 dma-names = "txdma", "rxdma";
25 compatible: "arm,dma-pl330"
27 include: dma-controller.yaml
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| D | st,stm32-bdma.yaml | 11 described in the dma.txt file, using a four-cell specifier for each
17 -bit 6-7 : Direction (see dma.h)
48 bdma1: dma-controller@58025400 {
52 dma-requests = <7>;
61 dma-names = "dmamux";
66 include: dma-controller.yaml
79 dma-offset:
83 for 1st dma instance, offset is 0,
84 for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
85 for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
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| D | intel,adsp-hda.yaml | 4 # Common fields for Intel ADSP HDA DMA controllers
6 include: dma-controller.yaml
12 dma-channels:
15 "#dma-cells":
18 "dma-buf-addr-alignment":
21 "dma-buf-size-alignment":
24 "dma-copy-alignment":
27 dma-cells:
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| D | st,stm32u5-dma.yaml | 5 STM32 DMA controller for the stm32U5 soc family
7 It is present on stm32U5 devices as a GP DMA
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
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| D | infineon,xmc4xxx-dma.yaml | 5 XMC4xxx DMA Controller
7 compatible: "infineon,xmc4xxx-dma"
9 include: dma-controller.yaml
18 dma-channels:
20 description: Number of DMA channels supported by the controller
22 "#dma-cells":
25 dma-cells:
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| /Zephyr-Core-3.5.0/tests/boards/intel_adsp/hda/src/ |
| D | dma.c | 9 #include <zephyr/drivers/dma.h>
39 * Tests host input streams with the DMA API
46 const struct device *dma; in ZTEST() local
70 dma = DEVICE_DT_GET(DT_NODELABEL(hda_host_in)); in ZTEST()
71 zassert_true(device_is_ready(dma), "DMA device is not ready"); in ZTEST()
73 channel = dma_request_channel(dma, NULL); in ZTEST()
74 zassert_true(channel >= 0, "Expected a valid DMA channel"); in ZTEST()
75 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dma channel"); in ZTEST()
96 res = dma_config(dma, channel, &dma_cfg); in ZTEST()
97 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dsp dma config"); in ZTEST()
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| /Zephyr-Core-3.5.0/tests/drivers/dma/loop_transfer/src/ |
| D | test_dma_loop.c | 1 /* dma.c - DMA test source file */
12 * @brief Verify zephyr dma memory to memory transfer loops
15 * -# Set dma channel configuration including source/dest addr, burstlen
27 #include <zephyr/drivers/dma.h>
40 __attribute__((__section__(CONFIG_DMA_LOOP_TRANSFER_SRAM_SECTION".dma")));
42 /* this src memory shall be in RAM to support usingas a DMA source pointer.*/
83 zassert_false(status < 0, "DMA could not proceed, an error occurred\n"); in dma_user_callback()
96 static int test_loop(const struct device *dma) in test_loop() argument
101 TC_PRINT("DMA memory to memory transfer started\n"); in test_loop()
111 if (!device_is_ready(dma)) { in test_loop()
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| /Zephyr-Core-3.5.0/tests/boards/altera_max10/msgdma/src/ |
| D | dma.c | 11 #include <zephyr/drivers/dma.h>
33 TC_PRINT("DMA completed successfully\n"); in dma_user_callback()
36 TC_PRINT("DMA error occurred!! (%d)\n", status); in dma_user_callback()
43 const struct device *dma; in ZTEST() local
47 dma = DEVICE_DT_GET(DT_NODELABEL(dma)); in ZTEST()
48 __ASSERT_NO_MSG(device_is_ready(dma)); in ZTEST()
55 /* Init DMA config info */ in ZTEST()
71 /* Init DMA descriptor info */ in ZTEST()
76 /* Configure DMA */ in ZTEST()
77 zassert_true(dma_config(dma, chan_id, &dma_cfg) == 0, in ZTEST()
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| /Zephyr-Core-3.5.0/include/zephyr/devicetree/ |
| D | dma.h | 3 * @brief DMA Devicetree macro public API header file.
20 * @defgroup devicetree-dmas Devicetree DMA API
26 * @brief Get the node identifier for the DMA controller from a
31 * dma1: dma@... { ... };
33 * dma2: dma@... { ... };
47 * @return the node identifier for the DMA controller referenced at
54 * @brief Get the node identifier for the DMA controller from a
59 * dma1: dma@... { ... };
61 * dma2: dma@... { ... };
66 * dma-names = "tx", "rx";
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | infineon,xmc4xxx-spi.yaml | 33 IRQ number and priority to use for interrupt driven SPI. If DMA is not used (enabled using
35 set. When using DMA, two interrupts labelled "tx" and "rx" must be set.
43 Optional TX & RX dma specifiers.
49 The parameters in the dma entry are: dma device phandle, dma channel, dma priority (0 is
50 lowest and 7 is highest), and an opaque entry for the dma line routing parameters set
53 1. Select a dma device and a free dma channel.
54 1. Select a free dma line. dma0 device can only connect to lines [0, 7] and
59 3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
63 The interrupt would map to SR1. From Table "DMA Request Source Selection", request_source
65 dma = <&dma0 3 4 XMC4XXX_SET_CONFIG(7,10) ... >;
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