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/Zephyr-latest/boards/nxp/lpcxpresso55s16/
Dlpcxpresso55s16.dts21 * allocate the SRAMs differently.
/Zephyr-latest/kernel/
Dmain_weak.c8 /* Linkers may treat weak functions differently if they are located within
/Zephyr-latest/tests/benchmarks/wait_queues/
DREADME.rst6 differently under different loads. This benchmark can be used to showcase how
/Zephyr-latest/doc/connectivity/networking/
Dnet_pkt_processing_stats.rst68 differently so there is slight difference because of rounding errors.
84 differently so there is slight difference because of rounding errors.
/Zephyr-latest/boards/nxp/lpcxpresso55s69/
Dlpcxpresso55s69_lpc55s69_cpu1.dts31 * allocate the SRAM0-4 differently.
Dlpcxpresso55s69_lpc55s69_cpu0.dts81 * allocate the SRAM0-4 differently.
/Zephyr-latest/drivers/serial/
Duart_native_tty_bottom.h20 /* Below enums are just differently namespaced copies of uart_config_* enums. Options that are not
/Zephyr-latest/dts/bindings/gpio/
Datmel-xplained-pro-header.yaml23 large boards), and EXT3. EXT4 to EXT7 can be placed differently depending
/Zephyr-latest/boards/nxp/lpcxpresso54114/
Dlpcxpresso54114_lpc54114_m4.dts55 * allocate the SRAM0-3 differently.
/Zephyr-latest/samples/application_development/code_relocation_nocopy/
DREADME.rst11 Differently from the code relocation sample, this sample is relocating the
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx-iomuxc.yaml47 # will need to initialize the pin configuration register differently based on
/Zephyr-latest/soc/mediatek/mt8xxx/
Dgen_img.py32 # doesn't appear to be SRAM. SRAM is mapped differently for different
/Zephyr-latest/tests/subsys/lorawan/frag_decoder/src/
Dfrag_encoder.c58 * Powers of 2 must be treated differently to make sure matrix content is close in lorawan_fec_parity_matrix_vector()
/Zephyr-latest/include/zephyr/net/
Dnet_linkaddr.h87 * handled differently than uint8_t addr[] and the fields are purposely
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947_mcxn947_cpu0.dtsi43 * allocate the SRAM0-7 differently.
/Zephyr-latest/doc/hardware/peripherals/sensor/
Dindex.rst34 :ref:`sensor-read-and-decode`. Triggers are handled entirely differently for
/Zephyr-latest/cmake/linker/lld/
Dtarget.cmake20 # Different generators deal with depfiles differently.
/Zephyr-latest/cmake/linker/arcmwdt/
Dtarget.cmake16 # Different generators deal with depfiles differently.
/Zephyr-latest/doc/services/storage/disk/
Daccess.rst32 each disk driver may handle differently, but it will always return
/Zephyr-latest/arch/xtensa/core/
Dmmu.c141 * allowed to cache PTEs differently across CPUs. We require in xtensa_init_paging()
/Zephyr-latest/kernel/include/
Dkswap.h45 * Stated differently: there's a chicken and egg bug with the question
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dmultiprocessing.c47 /* On cAVS v2.5, MP startup works differently. The core has in soc_start_core()
/Zephyr-latest/doc/connectivity/bluetooth/api/mesh/
Dblob.rst175 same Timeout Base value, but they calculate timeout differently.
/Zephyr-latest/doc/develop/languages/cpp/
Dindex.rst136 standardized. Standards can have ambiguities interpreted differently by
/Zephyr-latest/subsys/bluetooth/controller/util/
Dmfifo.h25 * Enqueuing is performed differently between APIs:

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