1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* Common dts file to enable supported features for CPU 0.
8 * This file is included by both the default variant
9 * which is run from internal flash and the QSPI variant.
10 */
11/dts-v1/;
12
13#include <nxp/nxp_mcxn94x.dtsi>
14#include "frdm_mcxn947.dtsi"
15
16/ {
17	cpus {
18		/delete-node/ cpu@1;
19	};
20
21	chosen {
22		zephyr,sram = &sram0;
23		zephyr,flash = &flash;
24		zephyr,flash-controller = &fmu;
25		zephyr,code-partition = &slot0_partition;
26		zephyr,uart-mcumgr = &flexcomm4_lpuart4;
27		zephyr,console = &flexcomm4_lpuart4;
28		zephyr,shell-uart = &flexcomm4_lpuart4;
29		zephyr,canbus = &flexcan0;
30		zephyr,code-cpu1-partition = &slot1_partition;
31	};
32
33	aliases{
34		watchdog0 = &wwdt0;
35		pwm-0 = &flexpwm1_pwm0;
36		pwm-1 = &sc_timer;
37		rtc = &rtc;
38	};
39};
40
41/*
42 * Default for this board is to allocate SRAM0-5 to cpu0 but the
43 * application can have an application specific device tree to
44 * allocate the SRAM0-7 differently.
45 *
46 * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
47 * for cpu1. This would require the value of sram0 to have a DT_SIZE_K
48 * of 384. You would have to make updates to cpu1 sram settings as well.
49 */
50&sram0 {
51	compatible = "mmio-sram";
52	reg = <0x20000000 DT_SIZE_K(320)>;
53};
54
55&mbox {
56	status = "okay";
57};
58
59&gpio4 {
60	status = "okay";
61};
62
63&gpio1 {
64	status = "okay";
65};
66
67&gpio0 {
68	status = "okay";
69};
70
71&gpio2 {
72	status = "okay";
73};
74
75&green_led {
76	status = "okay";
77};
78
79&red_led {
80	status = "okay";
81};
82
83&user_button_2 {
84	status = "okay";
85};
86
87&edma0 {
88	status = "okay";
89};
90
91&flexcomm1 {
92	status = "okay";
93};
94
95&flexcomm1_lpspi1 {
96	status = "okay";
97};
98
99&flexcomm2 {
100	status = "okay";
101};
102
103&flexcomm2_lpi2c2 {
104	status = "okay";
105};
106
107/*
108 *LPFLEXCOMM supports UART and I2C on the same instance, enable this for
109 * LFLEXCOMM2
110 */
111&flexcomm2_lpuart2 {
112	status = "okay";
113};
114
115&flexcomm4 {
116	status = "okay";
117};
118
119&flexcomm4_lpuart4 {
120	status = "okay";
121};
122
123&flexcomm7 {
124	status = "okay";
125};
126
127&flexcomm7_lpi2c7 {
128	status = "okay";
129};
130
131&flexspi {
132	status = "okay";
133};
134
135&w25q64jvssiq {
136	status = "okay";
137	partitions {
138		compatible = "fixed-partitions";
139		#address-cells = <1>;
140		#size-cells = <1>;
141		storage_partition: partition@0 {
142			label = "storage";
143			reg = <0x0 DT_SIZE_M(8)>;
144		};
145	};
146};
147
148&dac0 {
149	status = "okay";
150};
151
152&enet {
153	status = "okay";
154};
155
156&enet_mac {
157	status = "okay";
158};
159
160&enet_mdio {
161	status = "okay";
162};
163
164&wwdt0 {
165	status = "okay";
166};
167
168&flexpwm1_pwm0 {
169	status = "okay";
170};
171
172&flexcan0 {
173	status = "okay";
174};
175
176&ctimer0 {
177	status = "okay";
178};
179
180&usdhc0 {
181	status = "okay";
182	sdmmc {
183		compatible = "zephyr,sdmmc-disk";
184		disk-name = "SD";
185		status = "okay";
186	};
187};
188
189&vref {
190	status = "okay";
191};
192
193&lpadc0 {
194	status = "okay";
195};
196
197zephyr_udc0: &usb1 {
198	status = "okay";
199	phy-handle = <&usbphy1>;
200};
201
202&usbphy1 {
203	status = "okay";
204	tx-d-cal = <4>;
205	tx-cal-45-dp-ohms = <7>;
206	tx-cal-45-dm-ohms = <7>;
207};
208
209&lpcmp0 {
210	status = "okay";
211};
212
213&lptmr0 {
214	status = "okay";
215};
216
217&i3c1 {
218	status = "okay";
219};
220
221&flexio0 {
222	status = "okay";
223};
224
225&mrt0_channel0 {
226	status = "okay";
227};
228
229&rtc {
230	status = "okay";
231};
232
233&sc_timer {
234	status = "okay";
235};
236
237&sai1 {
238	status = "okay";
239};
240&sai0 {
241	status = "okay";
242};
243