Searched full:deasserted (Results 1 – 10 of 10) sorted by relevance
34 deasserted. If not set, no additional delay is inserted.
61 remain deasserted after issuing DPD before the chip will enter72 remain deasserted after issuing RDPD before the chip will exit
96 /* Canceling response since CS deasserted and output NOT_READY byte */723 * End of data for read/write transaction. i.e. SHI_CS is deasserted. in shi_npcx_isr()726 * EOR has the limitation that it will not be set even if the SHI_CS is deasserted without in shi_npcx_isr()728 * deasserted regardless of SPI clocks. in shi_npcx_isr()
334 /* CS# is deasserted, so write clear all slave status */ in shi_ite_int_handler()
658 /* CS deasserted. Setup for the next transaction */ in gpio_cb_nss()
453 * read chunk of data to get the IRQ_N negated (deasserted). in lan865x_int_thread()462 * OPEN Alliance 10BASE-T1x standard it is deasserted when first in lan865x_int_thread()
606 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_qspi_write()687 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_qspi_erase()
1009 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_xspi_erase()1288 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_xspi_write()
1180 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_ospi_erase()1451 /* Abort ongoing transfer to force CS high/BUSY deasserted */ in flash_stm32_ospi_write()
35 * * When CSn is deasserted the device enters a standby mode.
