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/Zephyr-latest/boards/nordic/nrf54h20dk/
Dnrf54h20dk_nrf54h20-ipc_conf.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 cpusec_cpuapp_ipc: ipc-1-2 {
10 compatible = "zephyr,ipc-icmsg";
12 dcache-alignment = <32>;
17 cpusec_cpurad_ipc: ipc-1-3 {
18 compatible = "zephyr,ipc-icmsg";
20 dcache-alignment = <32>;
25 cpuapp_cpurad_ipc: ipc-2-3 {
26 compatible = "zephyr,ipc-icbmsg";
27 dcache-alignment = <32>;
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/Zephyr-latest/boards/nordic/nrf9280pdk/
Dnrf9280pdk_nrf9280-ipc_conf.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 cpusec_cpuapp_ipc: ipc-1-2 {
10 compatible = "zephyr,ipc-icmsg";
12 dcache-alignment = <32>;
17 cpusec_cpurad_ipc: ipc-1-3 {
18 compatible = "zephyr,ipc-icmsg";
20 dcache-alignment = <32>;
25 cpuapp_cpurad_ipc: ipc-2-3 {
26 compatible = "zephyr,ipc-icbmsg";
27 dcache-alignment = <32>;
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/Zephyr-latest/dts/bindings/ipc/
Dzephyr,ipc-icmsg.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "zephyr,ipc-icmsg"
14 tx-region:
19 rx-region:
24 dcache-alignment:
27 Data cache alignment. If any side of the communication uses cache on
28 rx-region/tx-region this property must be the biggest value of the
29 invalidation or the write-back size for both sides of the communication.
34 Side B: 32 Bytes write-back size, 16 Bytes invalidation size
35 dcache-alignment = <32>; for both
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/Zephyr-latest/soc/andestech/ae350/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
19 select CACHE_MANAGEMENT if DCACHE
89 a look-up table and replaces suitable 32-bit instructions with
90 the 16-bit "exec.it <INDEX>".
100 matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
101 (power-of-two alignment).
108 Minimum size (and alignment) of an PMA region. Use this symbol
109 to guarantee minimum size and alignment of PMA regions.
117 depends on DCACHE
120 between cache and external non-caching master, such as DMA
/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
28 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
40 Make sure that you set correct value of the ``dcache-alignment``.
46 .. code-block:: devicetree
48 reserved-memory {
60 compatible = "zephyr,ipc-icmsg";
61 dcache-alignment = <32>;
62 tx-region = <&tx>;
63 rx-region = <&rx>;
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Dipc_service_icbmsg.rst11 …ming some common problems with other backends (mostly related to multithread access and zero-copy).
18 One is reserved for the ICMsg and the other contains equal-sized blocks.
26 For the zero-copy case, this is done by the caller, otherwise, it is copied automatically.
43 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
44 …This must be the largest value of the invalidation or the write-back size for both sides of the co…
46 * Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance.
48 * Define the number of allocable blocks for each region with ``tx-blocks`` and ``rx-blocks``.
54 Make sure that you set correct value of the ``dcache-alignment``.
60 .. code-block:: devicetree
62 reserved-memory {
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/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
25 compatible = "zephyr,ipc-icmsg";
26 dcache-alignment = <32>;
27 tx-region = <&sram_tx>;
28 rx-region = <&sram_rx>;
30 mbox-names = "rx", "tx";
Dnrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay4 * SPDX-License-Identifier: Apache-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
25 compatible = "zephyr,ipc-icbmsg";
26 dcache-alignment = <32>;
27 tx-region = <&sram_tx>;
28 rx-region = <&sram_rx>;
29 tx-blocks = <16>;
30 rx-blocks = <18>;
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/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/remote/boards/
Dnrf54l15dk_nrf54l15_cpuflpr.overlay4 * SPDX-License-Identifier: Apache-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
25 compatible = "zephyr,ipc-icmsg";
26 dcache-alignment = <32>;
27 tx-region = <&sram_tx>;
28 rx-region = <&sram_rx>;
30 mbox-names = "rx", "tx";
45 /delete-property/ hw-flow-control;
Dnrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay4 * SPDX-License-Identifier: Apache-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
25 compatible = "zephyr,ipc-icbmsg";
26 dcache-alignment = <32>;
27 tx-region = <&sram_tx>;
28 rx-region = <&sram_rx>;
29 tx-blocks = <18>;
30 rx-blocks = <16>;
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/Zephyr-latest/doc/hardware/cache/
Dguide.rst15 The information here assumes that the architecture-specific MPU support is
16 enabled. See the architecture-specific documentation for details.
45 ---------------------------------
52 * :kconfig:option:`CONFIG_DCACHE`: DCACHE control enabled in Zephyr.
59 -------------------------------------
68 * :kconfig:option:`CONFIG_DCACHE`: DCACHE control enabled in Zephyr.
70 * :kconfig:option:`CONFIG_MEM_ATTR`: enable the ``mem-attr`` library for
81 .. code-block:: c
95 -------------------------------------------
107 * :kconfig:option:`CONFIG_DCACHE`: DCACHE control enabled in Zephyr.
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/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
Dsoc.c3 * SPDX-License-Identifier: Apache-2.0
64 /* Platform-specific early initialization */
69 * When coming out of u-boot rather than downloading the Zephyr binary in soc_reset_hook()
70 * via JTAG, a few things modified by u-boot have to be re-set to a in soc_reset_hook()
73 * - u-boot places the exception vectors somewhere in RAM and then in soc_reset_hook()
79 * - u-boot sets the following bits in the SCTLR register: in soc_reset_hook()
80 * - [I] ICache enable in soc_reset_hook()
81 * - [C] DCache enable in soc_reset_hook()
82 * - [Z] Branch prediction enable in soc_reset_hook()
83 * - [A] Enforce strict alignment enable in soc_reset_hook()
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/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
Dsoc.c3 * SPDX-License-Identifier: Apache-2.0
64 /* Platform-specific early initialization */
69 * When coming out of u-boot rather than downloading the Zephyr binary in soc_reset_hook()
70 * via JTAG, a few things modified by u-boot have to be re-set to a in soc_reset_hook()
73 * - u-boot places the exception vectors somewhere in RAM and then in soc_reset_hook()
79 * - u-boot sets the following bits in the SCTLR register: in soc_reset_hook()
80 * - [I] ICache enable in soc_reset_hook()
81 * - [C] DCache enable in soc_reset_hook()
82 * - [Z] Branch prediction enable in soc_reset_hook()
83 * - [A] Enforce strict alignment enable in soc_reset_hook()
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/Zephyr-latest/arch/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
195 # Hidden Kconfig option representing the default little-endian architecture
196 # This is just the opposite of BIG_ENDIAN and is used for non-negative
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/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.c3 * SPDX-License-Identifier: Apache-2.0
26 #define CDNSMMC_ADDRESS_MASK (CONFIG_SDHC_BUFFER_ALIGNMENT - 1)
59 return -ENXIO; in sdhc_cdns_write_phy_reg()
71 return -ETIMEDOUT; in sdhc_cdns_wait_ics()
93 return -ETIMEDOUT; in sdhc_cdns_card_present()
117 * with input value- mode sd_ds,
128 sdhc_cdns_combo_phy_reg->cp_clk_wr_delay = 0; in cdns_sdhc_set_sdmmc_params()
129 sdhc_cdns_combo_phy_reg->cp_clk_wrdqs_delay = 0; in cdns_sdhc_set_sdmmc_params()
130 sdhc_cdns_combo_phy_reg->cp_data_select_oe_end = 1; in cdns_sdhc_set_sdmmc_params()
131 sdhc_cdns_combo_phy_reg->cp_dll_bypass_mode = 1; in cdns_sdhc_set_sdmmc_params()
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/Zephyr-latest/arch/arm64/core/
Dmmu.c7 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/linker/linker-defs.h>
63 unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; in table_index()
78 MMU_DEBUG("table [%d]%p: usage %#x -> %#x\n", i, table, prev_count, new_count); in table_usage()
101 table_usage(table, -ref_unit); in dec_table_ref()
175 bool aligned = (desc & PTE_PHYSADDR_MASK & (level_size - 1)) == 0; in is_desc_block_aligned()
200 MMU_DEBUG("---\n"); in debug_show_pte()
218 MMU_DEBUG("[paged-out] "); in debug_show_pte()
225 MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_RO) ? "-RO" : "-RW"); in debug_show_pte()
226 MMU_DEBUG((*pte & PTE_BLOCK_DESC_NS) ? "-NS" : "-S"); in debug_show_pte()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
249 newly created informational-only callback struct :c:struct:`bt_conn_auth_info_cb`.
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Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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